MAX16047_09 Datasheet, PDF (32/61 Pages) Maxim Integrated Products – 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers

12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Closed-Loop Tracking
The MAX16047/MAX16049 track up to four voltages
during any time slot except Slot 0 and Slot 12.
Configure GPIO1–GPIO4 as sense line inputs (INS_) to
monitor tracking voltages. Configure GPIO6 as
FAULTPU to indicate tracking faults, if desired. See the
General-Purpose Inputs/Outputs section for information
on configuring GPIOs.
For closed-loop tracking, use MON1, EN_OUT1, and
INS1 together to form a complete channel. Use MON2,
EN_OUT2, and INS2 to form a second complete chan-
nel. Use MON3, EN_OUT3, and INS3 together to form a
third channel; and use MON4, EN_OUT4, and INS4 to
form a fourth channel.
When configured for closed-loop tracking, assign each
EN_OUT_ to the same slot as its associated single
monitoring input (MON_). For example, if EN_OUT2 is
assigned to Slot 3, the monitoring input is MON2 and
must be assigned to Slot 3. This is because the MON_
input, checked at the start of the slot, must be valid
before tracking can begin. Tracking begins immediate-
ly and must finish before the power-up fault timeout
expires, or a fault will trigger. EN_OUT_ configured for
closed-loop tracking cannot be assigned to Slot 0.
The tracking control circuitry includes a ramp generator
and a comparator control block for each tracked volt-
age (see the Functional Diagram and Figure 5). The
comparator control block compares each INS_ voltage
with a control voltage ramp. If INS_ voltages vary from
the control ramp by more than 150mV (typ), the com-
parator control block signals an alert that dynamically
stops the ramp until the slow INS_ voltage rises to with-
in the allowed voltage window. The total tracking time is
extended under these conditions, but must still com-
plete within the selected power-up/power-down fault
timeout. The power-up/power-down tracking fault time-
out period is adjustable through r4Eh[3:0].
A voltage difference between any two tracking INS_
voltages exceeding 330mV generates a tracking fault,
forcing all EN_OUT_ voltages low and generating a
fault log. If configured as FAULTPU, GPIO6 asserts
when a tracking fault occurs.
The comparator control blocks also monitor INS_ volt-
ages with respect to input (MON_) voltages. Under nor-
mal conditions each INS_ tracks the control ramp until
the INS_ voltages reach the configured power-good
V_IN
MON_
ADC MUX
LOGIC
REFERENCE
RAMP
V_OUT
EN_OUT_ INS_
GATE
DRIVE
V_{TH_PG}
100Ω
Figure 5. Closed-Loop Tracking
(PG) thresholds, set as a programmable percentage of
the MON_ voltage. Use register r64h to set the PG
thresholds (Table 14). Once PG is detected, the exter-
nal n-channel FET saturates with 5V (typ) applied
between gate and source. The slew rate for the control
ramp is programmable from 100V/s to 800V/s in
r4Fh[5:4] (see Table 12).
Power-down initiates when EN is forced low or when
the Software Enable bit in r4Dh[0] is set to ‘1.’ If the
Reverse Sequence bit is set (r54h[4]) INS_ voltages fol-
low a falling reference ramp to ground as long as
MON_ voltages remain high enough to supply the
required voltage/current. If a monitored voltage drops
faster than the control ramp voltage or the correspond-
ing MON_ voltage falls too quickly, power-down track-
ing operation is terminated and all EN_OUT_ voltages
are immediately forced to ground. If the Reverse
Sequence bit is set to ‘0,’ all EN_OUT_ voltages are
forced low simultaneously.
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