MAX1661-MAX1663 Datasheet, PDF (3/16 Pages) Maxim Integrated Products – Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface

Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Controllers with SMBus Interface
ELECTRICAL CHARACTERISTICS (continued)
(V_CC = +2.7V to +5.5V, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are for T_A = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Start-Condition Setup Time
t_SU:STA
Measured from 90% of the SMBCLK rising
edge to 90% of the SMBDATA falling edge
4.7
Measured from 10% of the falling edge
Start-Condition Hold Time
t_HD:STA of SMBDATA to 90% of the falling edge of
4
SMBCLK
SMBus Stop-Condition Setup
Time
t_SU:STO
Measured from 90% of the rising edge
of SMBCLK to 10% of the rising edge of
SMBDATA
4
SMBDATA Valid to SMBCLK
Rising Edge Time, Slave
Clocking in Data
t_SU:DAT
10% or 90% of SMBDATA
to 10% of the rising edge
of SMBCLK
V_CC = 4.5V
to 5.5V
V_CC = 2.7V
to 4.5V
500
1000
SMBCLK Falling Edge to
SMBDATA Transition Hold Time
t_HD:DAT
(Notes 4, 5)
0
SMBCLK Falling Edge to
SMBus Data Valid Time
SMBus Bus-Free Time
SMBus Write to I/O_
Propagation Delay
t_DV
Tested with a 10kΩ pull-up resistor on
SMBDATA (Note 6)
t_BUF Between stop and start conditions (Note 7)
4.7
t_P:I/O
Measured from SMBCLK rising edge to 10%
or 90% of I/O (Note 4)
100
I/O Data Valid to SMBCLK
Rising-Edge Setup Time
t_SU:I/O
Measured from 10% or 90% of V_I/O to 10% of
the rising edge of SMBCLK (Note 8)
15
I/O Data Hold Time
t_HD:I/O (Note 8)
0
START-STOP Software-Interrupt
Pulse Width
t_LOW:SS
Measured from the 10% point of the falling
edge of SMBDATA to the 10% point of the
rising edge of SMBDATA (Note 7)
10
15
MAX UNITS
µs
µs
µs
ns
µs
1
µs
µs
ns
µs
µs
30
µs
Note 1: Specifications from 0°C to -40°C are guaranteed by design, not production tested.
Note 2: Supply current is specified for static state only.
Note 3: The SMBus logic block is a static design that works with clock frequencies down to DC. While slow operation is possible, it
violates the 10kHz minimum clock frequency of the SMBus specifications, and may monopolize the bus.
Note 4: Refer to Figures 2a and 2b for SMBus timing parameter definitions (write and read diagrams).
Note 5: A transition must internally provide a hold time of 300ns to accommodate for the undefined region of the falling edge.
Note 6: Refer to Figure 3 for the acknowledge timing diagram and t_DV parameter definition.
Note 7: Refer to Figure 5 for START-STOP interrupt timing diagrams and parameter definitions.
Note 8: Refer to Figure 4 for I/O setup and hold timing parameter definitions.
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