MAX1034_12 Datasheet, PDF (3/31 Pages) Maxim Integrated Products – 8-/4-Channel, ±VREF Multirange Inputs,Serial 14-Bit ADCs

8-/4-Channel, ±V_REF Multirange Inputs,
Serial 14-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD1 = V_AVDD2 = V_DVDD = V_DVDDO = 5V, V_AGND1 = V_DGND = V_DGNDO = V_AGND2 = V_AGND3 = 0V, f_CLK = 3.5MHz (50% duty cycle),
external clock mode, V_REF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±V_REF),
C_DOUT = 50pF, C_SSTRB = 50pF, T_A = -40°C to +85°C, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS f_{IN(SINE-WAVE)} = 5kHz, V_IN = FSR - 0.05dB, f_SAMPLE = 130ksps (Notes 1, 2)
Differential inputs, FSR = 2 x V_REF
84.5
Signal-to-Noise Plus Distortion
SINAD
Single-ended inputs, FSR = V_REF
Single-ended inputs, FSR = V_REF/2
84
dB
82.5
Single-ended inputs, FSR = V_REF/4
79
80.5
Differential inputs, FSR = 2 x V_REF
84.5
Signal-to-Noise Ratio
SNR
Single-ended inputs, FSR = V_REF
Single-ended inputs, FSR = V_REF/2
84
dB
82.5
Single-ended inputs, FSR = V_REF/4
80.5
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-98
dB
Spurious-Free Dynamic Range
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
CONVERSION RATE
SFDR
t_AD
t_AJ
Figure 21
Figure 21
92
99
dB
15
ns
100
ps
105
dB
External clock mode, Figure 2
Byte-Wide Throughput Rate
f_SAMPLE External acquisition mode, Figure 3
Internal clock mode, Figure 4
ANALOG INPUTS (CH0–CH3 MAX1035, CH0–CH7 MAX1034, AGND1)
Small-Signal Bandwidth
Full-Power Bandwidth
All input ranges, V_IN = 100mV_P-P (Note 2)
All input ranges, V_IN = 4V_P-P (Note 2)
R[2:1] = 001
R[2:1] = 010
R[2:1] = 011
Input Voltage Range (Table 6)
V_{CH_} R[2:1] = 100
R[2:1] = 101
R[2:1] = 110
R[2:1] = 111
114
84
ksps
106
-V_REF/4
-V_REF/2
0
-V_REF/2
-V_REF
0
-V_REF
2
MHz
700
kHz
+V_REF/4
0
+V_REF/2
+V_REF/2 V
0
+V_REF
+V_REF
True-Differential Analog
Common-Mode Voltage Range
Common-Mode Rejection Ratio
Input Current
Input Capacitance
Input Resistance
V_CMDR DIF/SGL = 1 (Note 4)
-4.75
+5.50
V
CMRR DIF/SGL = 1, input voltage range = ±V_REF/4
75
dB
I_{CH_}
-V_REF < V_{CH_} < +V_REF
-1500
+650
µA
C_{CH_}
5
pF
R_{CH_}
6
kΩ
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