MAX1034_12 Datasheet, PDF (19/31 Pages) Maxim Integrated Products – 8-/4-Channel, ±VREF Multirange Inputs,Serial 14-Bit ADCs

8-/4-Channel, ±V_REF Multirange Inputs,
Serial 14-Bit ADCs
+V_REF
+3/4 V_REF
+V_REF/2
+V_REF/4
0
-V_REF/4
-V_REF/2
-3/4 V_REF
-V_REF
INPUT RANGE SELECTION BITS, R[2:0]
EACH INPUT IS FAULT TOLERANT TO ±6V.
Figure 7. Single-Ended Input Voltage Ranges
Digital Interface
The MAX1034/MAX1035 feature a serial interface that is
compatible with SPI/QSPI and MICROWIRE devices.
DIN, DOUT, SCLK, CS, and SSTRB facilitate bidirection-
al communication between the MAX1034/MAX1035 and
the master at SCLK rates up to 10MHz (internal clock
mode, mode 2), 3.67MHz (external clock mode, mode
0), or 4.39MHz (external acquisition mode, mode 1).
The master, typically a microcontroller, should use the
CPOL = 0, CPHA = 0, SPI transfer format, as shown in
the timing diagrams of Figures 2, 3, and 4.
The digital interface is used to:
• Select single-ended or true-differential input channel
configurations
• Select the unipolar or bipolar input range
• Select the mode of operation:
External clock (mode 0)
External acquisition (mode 1)
Internal clock (mode 2)
Reset (mode 4)
Partial power-down (mode 6)
Full power-down (mode 7)
• Initiate conversions and read results
+V_REF
+3/2 V_REF
+V_REF
+V_REF/2
0
-V_REF/2
-V_REF
-3/2 V_REF
-2 x V_REF
INPUT RANGE SELECTION BITS, R[2:0]
EACH INPUT IS FAULT TOLERANT TO ±6V.
Figure 8. Differential Input Voltage Ranges
Chip Select (CS)
CS enables communication with the MAX1034/MAX1035.
When CS is low, data is clocked into the device from DIN
on the rising edge of SCLK and data is clocked out of
DOUT on the falling edge of SCLK. When CS is high,
activity on SCLK and DIN is ignored and DOUT is high
impedance allowing DOUT to be shared with other
peripherals. SSTRB is never high impedance and there-
fore cannot be shared with other peripherals.
Serial-Strobe Output (SSTRB)
As shown in Figures 3 and 4, the SSTRB transitions high
to indicate that the ADC has completed a conversion
and results are ready to be read by the master. SSTRB
remains low in the external clock mode (Figure 2) and
consequently may be left unconnected. SSTRB is driven
high or low regardless of the state of CS, therefore
SSTRB cannot be shared with other peripherals.
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