DS2156 Datasheet, PDF (3/265 Pages) Dallas Semiconductor – T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

DS2156
13.2.1 T1 Operation ........................................................................................................................................85
13.2.2 E1 Operation ........................................................................................................................................85
13.3 FRAMES OUT-OF-SYNC COUNT REGISTER (FOSCR).................................................................. 86
13.3.1 T1 Operation ........................................................................................................................................86
13.3.2 E1 Operation ........................................................................................................................................86
13.4 E-BIT COUNTER (EBCR) ........................................................................................................... 87
14. DS0 MONITORING FUNCTION..................................................................................... 88
15. SIGNALING OPERATION ............................................................................................. 90
15.1 RECEIVE SIGNALING .................................................................................................................. 90
15.1.1 Processor-Based Signaling..................................................................................................................90
15.1.2 Hardware-Based Receive Signaling ....................................................................................................91
15.2 TRANSMIT SIGNALING ................................................................................................................ 96
15.2.1 Processor-Based Mode .......................................................................................................................96
15.2.2 Software Signaling Insertion-Enable Registers, E1 CAS Mode ........................................................100
15.2.3 Software Signaling Insertion-Enable Registers, T1 Mode .................................................................102
15.2.4 Hardware-Based Mode ......................................................................................................................102
16. PER-CHANNEL IDLE CODE GENERATION .............................................................. 103
16.1 IDLE-CODE PROGRAMMING EXAMPLES..................................................................................... 104
17. CHANNEL BLOCKING REGISTERS .......................................................................... 108
18. ELASTIC STORES OPERATION ................................................................................ 111
18.1 RECEIVE SIDE ......................................................................................................................... 114
18.1.1 T1 Mode .............................................................................................................................................114
18.1.2 E1 Mode.............................................................................................................................................114
18.2 TRANSMIT SIDE ....................................................................................................................... 114
18.2.1 T1 Mode .............................................................................................................................................115
18.2.2 E1 Mode.............................................................................................................................................115
18.3 ELASTIC STORES INITIALIZATION .............................................................................................. 115
18.4 MINIMUM DELAY MODE ............................................................................................................ 115
19. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY).................................. 116
20. T1 BIT-ORIENTED CODE (BOC) CONTROLLER ...................................................... 117
20.1 TRANSMIT BOC ....................................................................................................................... 117
Transmit a BOC................................................................................................................................................117
20.2 RECEIVE BOC ......................................................................................................................... 117
Receive a BOC.................................................................................................................................................117
21. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY).......... 120
21.1 METHOD 1: HARDWARE SCHEME ............................................................................................. 120
21.2 METHOD 2: INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME ...................................... 120
21.3 METHOD 3: INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME ................................ 123
22. HDLC CONTROLLERS ............................................................................................... 133
22.1 BASIC OPERATION DETAILS ..................................................................................................... 133
22.2 HDLC CONFIGURATION ........................................................................................................... 133
22.2.1 FIFO Control ......................................................................................................................................137
22.3 HDLC MAPPING ...................................................................................................................... 138
22.3.1 Receive ..............................................................................................................................................138
22.3.2 Transmit .............................................................................................................................................140
22.3.3 FIFO Information ................................................................................................................................145
22.3.4 Receive Packet-Bytes Available ........................................................................................................145
22.3.5 HDLC FIFOs ......................................................................................................................................146
22.4 RECEIVE HDLC CODE EXAMPLE.............................................................................................. 147
22.5 LEGACY FDL SUPPORT (T1 MODE).......................................................................................... 147
22.5.1 Overview ............................................................................................................................................147
22.5.2 Receive Section .................................................................................................................................147
22.5.3 Transmit Section ................................................................................................................................149
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