DS2156 Datasheet, PDF (260/265 Pages) Dallas Semiconductor – T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Figure 36-11. Transmit-Side Timing
tR
TCLK
TESO
TSER / TSIG /
TDATA
TCHCLK
TCHBLK
TSYNC1
TSYNC2
TLCLK5
TLINK
tF
t _D1
t _D2
tCP
tCL tCH
t _SU
tHD
tD2
t _SU
t _D2
t _HD
t _D2
tHD
t _SU
DS2156
Note 1: TSYNC is in the output mode (IOCR1.1 = 1).
Note 2: TSYNC is in the input mode (IOCR1.1 = 0).
Note 3: TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.
Note 4: TCHCLK and TCHBLK are synchronous with TCLK when the transmit-side elastic store is disabled.
Note 5: In E1 mode, TLINK is only sampled during Sa bit locations as defined in E1TCR2; no relationship between TLCLK/TLINK and TSYNC
is implied.
260 of 265