DS1086LPMB1 Datasheet, PDF (3/8 Pages) Maxim Integrated Products – DS1086LPMB1 Peripheral Module

DS1086LPMB1 Peripheral Module
External Control Signals
The IC implements pins to control output enable (OE),
power-down (PDN), and dither enable (SPRD). These
pins can be controlled either by the host (through the
Pmod connector) or by external circuitry through the
5-pin output connector. In cases where one or more
of these signals is driven from an external source, 1kI
resistors R3, R4, and R5 limit the current to/from the
host. However, this also increases the apparent load to
the external driving source. If the external source is inca-
pable of driving this load (1kI||4.7kI), the signal(s) from
the host should either be put into three-state (open) or
resistors R3, R4, and/or R5 should be removed.
The J3 connector provides the output signal as well as
external inputs to the control signals. Note that the con-
trol lines from the host (SPRD, PND, OE) must either be
three-stated or the external control signals must be able
to drive the additional load. See Table 3.
Software and FPGA Code
Example software and drivers are available that execute
directly without modification on several FPGA devel-
opment boards that support an integrated or synthe-
sized microprocessor. These boards include the Digilent
Nexys 3, Avnet LX9, and Avnet ZEDBoard, although
other platforms can be added over time. Maxim provides
complete Xilinx ISE projects containing HDL, Platform
Table 2. Connector J2 (I²C Expansion)
PIN SIGNAL
DESCRIPTION
1
SCL I²C serial clock
2
SDA I²C serial data
3
GND Ground
4
VCC Power supply
5
SCL I²C serial clock
6
SDA I²C serial data
7
GND Ground
8
VCC Power supply
Studio, and SDK projects. In addition, a synthesized bit
stream, ready for FPGA download, is provided for the
demonstration application.
The software project (for the SDK) contains several
source files intended to accelerate customer evalu-
ation and design. These include a base application
(maximModules.c) that demonstrates module function-
ality and uses an API interface (maximDeviceSpecific
Utilities.c) to set and access Maxim device functions
within a specific module.
The source code is written in standard ANSI C format, and
all API documentation including theory/operation, register
description, and function prototypes are documented in
the API interface file (maximDeviceSpecificUtilities.h & .c).
The complete software kit is available for download
www.maxim-ic.com. Quick start instructions are also
available as a separate document.
Table 3. Connector J3 (External Interface)
PIN SIGNAL
DESCRIPTION
Oscillator output. The output frequency is
1
OUT set by the OFFSET, DAC, and prescaler
registers.
2
GND Ground
Dither enable. When the pin is high, the
3
SPRD dither is enabled. When the pin is low,
the dither is disabled.
Power-down. When the pin is high, the
4
PDN
output buffer is enabled. When the pin
is low, the master oscillator is disabled
(power-down mode).
Output enable. When the pin is high,
5
OE
the output buffer is enabled. When the
pin is low, the output is disabled but the
master oscillator is still on.
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