MAX1402 Datasheet, PDF (29/40 Pages) Maxim Integrated Products – +5V, 18-Bit, Low-Power, Multichannel, Oversampling Sigma-Delta ADC

+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
The noise shown in Table 16 is composed of device
noise and quantization noise. The device noise is rela-
tively low, but becomes the limiting noise source for
high gain settings. The quantization noise is dependent
on the notch frequency and becomes the dominant
noise source as the notch frequency is increased.
Offset-Correction DAC
The MAX1402 provides a coarse (3-bit plus sign) offset-
correction DAC at the modulator input. Use this DAC to
remove the offset component in the input signal, allow-
ing the ADC to operate on a more sensitive range. The
DAC offsets up to ±116.7% of the selected range in
±16.7% increments for unipolar mode and up to
±58.3% of the selected range in ±8.3% increments for
bipolar mode. When a DAC value of 0 is selected, the
DAC is completely disconnected from the modulator
inputs and does not contribute any noise. Figures 7
and 9 show the effect of the DAC codes on the input
range and transfer function.
Clock Oscillator
The clock oscillator may be used with an external crystal
(or resonator) connected between CLKIN and CLKOUT,
or may be driven directly by an external oscillator at
CLKIN with CLKOUT left unconnected. In normal oper-
ating mode, the MAX1402 is specified for operation with
CLKIN at either 1.024MHz (CLK = 0) or 2.4576MHz
(CLK = 1, default). When operated at these frequencies,
the part may be programmed to produce frequency
response nulls at the local line frequency (either 60Hz or
50Hz) and the associated line harmonics.
In standby mode (STBY = 1) all circuitry, with the
exception of the serial interface and the clock oscillator,
is powered down. The interface consumes minimal
power with a static SCLK. Enter power-down mode
(including the oscillator) by setting the FULLPD bit in
the special-function register. When exiting a full-power
shutdown, perform a hardware reset or a software reset
after the master clock signal is established (typically
10ms when using the on-board oscillator with an exter-
nal crystal) to ensure that any potentially corrupted reg-
isters are cleared.
It is often helpful to use higher-frequency crystals or
resonators, especially for surface-mount applications
where the result may be reduced PC board area for the
oscillator component and a lower price or better com-
ponent availability. Also, it may be necessary to oper-
ate the part with a clock source whose duty cycle is not
close to 50%. In either case, the MAX1402 can operate
with a master clock frequency of up to 5MHz, and
includes an internal divide-by-2 prescaler to restore the
internal clock frequency to a range of up to 2.5MHz
with a 50% duty cycle. To activate this prescaler, set
the X2CLK bit in the control registers. Note that using
CLKIN frequencies above 2.5MHz in combination with
the X2CLK mode will result in a small increase in digital
supply current.
Digital Filter
The on-chip digital filter processes the 1-bit data
stream from the modulator using a SINC³ or SINC¹ fil-
ter. The SINC filters are conceptually simple, efficient,
and extremely flexible, especially where variable reso-
lution and data rates are required. Also, the filter notch
positions are easily controlled, since they are directly
related to the output data rate (1 / data word period).
The SINC¹ function results in a faster settling response
while retaining the same frequency response notches
as the default SINC³ filter. This allows the filter to settle
faster at the expense of resolution and quantization
noise. The SINC¹ filter settles in one data word period.
With 60Hz notches (60Hz data rate), the settling time
would be 1 / 60Hz or 16.7ms whereas the SINC³ filter
would settle in 3 / 60Hz or 50ms. Toggle between these
filter responses using the FAST bit in the global setup
register. Use SINC¹ mode for faster settling and switch
to SINC³ mode when full accuracy is required. Switch from
the SINC¹ to SINC³ mode by resetting the FAST bit low.
The DRDY signal will go false and will be reasserted
(V_{REF = 2.5V} (V_{REF = 1.25V}
PGA = 000) PGA = 000)
2.708V
13/6 V_REF/2^PGA
5.00V 2.50V
2 V_REF/2^PGA
4.503V 2.292V
11/6 V_REF/2^PGA
4.167V 2.083V
10/6 V_REF/2^PGA
3.750V 1.875V
9/6 V_REF/2^PGA
3.333V 1.667V
8/6 V_REF/2^PGA
2.917V 1.458V
2.50V 1.25V
2.083V 1.042V
1.667V 0.833V
1.25V 0.625V
0.833V 0.416V
0.416V 0.208V
0V
0V
-0.416V -0.208V
-0.833V -0.416V
-1.25V -0.625V
-1.667V -0.833V
-2.083V -1.042V
-2.50V -1.25V
-2.917V -1.458V
-3.333V -1.667V
MINIMMUINMIMINUPMMUATINX(PUIMU/BTUM=(U0/I)NBP=U1T)
7/6 V_REF/2^PGA
V_REF/2^PGA
5/6 V_REF/2^PGA
4/6 V_REF/2^PGA
3/6 V_REF/2^PGA
2/6 V_REF/2^PGA
1/6 V_REF/2^PGA
0
-1/6 V_REF/2^PGA
-2/6 V_REF/2^PGA
-3/6 V_REF/2^PGA
-4/6 V_REF/2^PGA
-5/6 V_REF/2^PGA
-V_REF/2^PGA
-7/6 V_REF/2^PGA
-8/6 V_REF/2^PGA
-3.750V -1.875V
-9/6 V_REF/2^PGA
-4.167V -2.083V
-10/6 V_REF/2^PGA
-4.503V -2.292V
-11/6 V_REF/2^PGA
-5.00V -2.50V
-2 V_REF/2^PGA
-2.708V
-13/6 V_REF/2^PGA
-7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7
D3: 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
D2: 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1
D1: 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1
D0: 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1
DAC CODE
Figure 9. Input Voltage Range vs. DAC Code
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