MAX1220_12 Datasheet, PDF (29/43 Pages) Maxim Integrated Products – 12-Bit, Multichannel ADCs/DACs with FIFO,Temperature Sensing, and GPIO Ports

12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
averaging as long as the AVGON bit, bit 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
disables averaging. For example, if AVGON = 1,
NAVG[1:0] = 00, NSCAN[1:0] = 11, and SCAN[1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
DAC Select Register
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 10) to set up the DAC inter-
face and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
Table 10. DAC Select Register
BIT
NAME
—
—
—
—
X
X
X
X
BIT
FUNCTION
7 (MSB) Set to zero to select DAC select register.
6 Set to zero to select DAC select register.
5 Set to zero to select DAC select register.
4 Set to one to select DAC select register.
3 Don’t care.
2 Don’t care.
1 Don’t care.
0 Don’t care.
Table 11. Reset Register
BIT
NAME
BIT
FUNCTION
— 7 (MSB) Set to zero to select ADC reset register.
—
6 Set to zero to select ADC reset register.
—
5 Set to zero to select ADC reset register.
—
4 Set to zero to select ADC reset register.
—
3 Set to one to select ADC reset register.
RESET
Set to zero to clear the FIFO only. Set to
2 one to set the device in its power-on
condition.
SLOW
1 Set to one to turn on slow mode.
Set to one to force internal bias block and
FBGON 0 (LSB) bandgap reference to be always powered
up.
byte controls the DAC serial interface. See Table 20
and the DAC Serial Interface section.
Reset Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or reset all registers (excluding the DAC
and GPIO registers) to their default states. When the
RESET bit in the reset register is set to 0, the FIFO is
cleared. Set the RESET bit to one to return all the
device registers to their default power-up state. All reg-
isters power up in state 00000000, except for the setup
register that powers up in clock mode 10 (CKSEL1 = 1
and REFSEL1 = 1). The DAC and GPIO registers are
not reset by writing to the reset register. Set the SLOW
bit to one to add a 15ns delay in the DOUT signal path
to provide a longer hold time. Writing a one to the
SLOW bit also clears the contents of the FIFO. Set the
FBGON bit to one to force the bias block and bandgap
reference to power up regardless of the state of the
DAC and activity of the ADC block. Setting the FBGON
bit high also removes the programmed wake-up delay
between conversions in clock modes 01 and 11.
Setting the FBGON bit high also clears the FIFO.
Table 12. GPIO Command Register
BIT NAME
—
—
—
—
—
—
GPIOSEL1
GPIOSEL2
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
FUNCTION
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
Set to zero to select GPIO register.
GPIO configuration bit.
GPIO write bit.
GPIOSEL1 GPIOSEL2
FUNCTION
GPIO configuration; written data is
1
1
entered in the GPIO configuration
register.
1
0
GPIO write; written data is entered
in the GPIO write register.
GPIO read; the next 8/16 SCLK
0
1
cycles transfer the state of all GPIO
drivers into DOUT.
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