MAX1220_12 Datasheet, PDF (20/43 Pages) Maxim Integrated Products – 12-Bit, Multichannel ADCs/DACs with FIFO,Temperature Sensing, and GPIO Ports

12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 1. Command Byte (MSB First)
REGISTER
NAME
Conversion
Setup
ADC
DAC Select
Reset
GPIO Configure
GPIO Write
GPIO Read
No Operation
X = Don’t care.
BIT 7
1
0
0
0
0
0
0
0
0
BIT 6
BIT 5
BIT 4
CHSEL3
1
0
0
0
0
0
0
0
CHSEL2
CKSEL1
1
0
0
0
0
0
0
CHSEL1
CKSEL0
AVGON
1
0
0
0
0
0
BIT 3
CHSEL0
REFSEL1
NAVG1
X
1
0
0
0
0
BIT 2
SCAN1
REFSEL0
NAVG0
X
RESET
0
0
0
0
BIT 1
BIT 0
SCAN0
DIFFSEL1
NSCAN1
X
SLOW
1
1
0
0
TEMP
DIFFSEL0
NSCAN0
X
FBGON
1
0
1
0
ADDITIONAL
NO. OF
BYTES
0
1
0
2
0
1 or 2
1 or 2
1 or 2
0
Write to the GPIOs by issuing a command byte to the
appropriate register. Writing to the MAX1220 GPIOs
requires 1 additional byte following the command byte.
Writing to the MAX1257/MAX1258 requires 2 additional
bytes following the command byte. See Tables 12–19
for details on GPIO configuration, writes, and reads.
See the GPIO Command section. Command bytes writ-
ten to the GPIOs on devices without GPIOs are ignored.
Power-Up Default State
The MAX1220/MAX1257/MAX1258 power up with all
blocks in shutdown (including the reference). All regis-
ters power up in state 00000000, except for the setup
register and the DAC input register. The setup register
powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
FFFh when RES_SEL is high and powers up to 000h
when RES_SEL is low.
12-Bit ADC
The MAX1220/MAX1257/MAX1258 ADCs use a fully
differential successive-approximation register (SAR)
conversion technique and on-chip track-and-hold (T/H)
circuitry to convert temperature and voltage signals into
12-bit digital results. The analog inputs accept both sin-
gle-ended and differential input signals. Single-ended
signals are converted using a unipolar transfer function,
and differential signals are converted using a selec-
table bipolar or unipolar transfer function. See the ADC
Transfer Functions section for more data.
ADC Clock Modes
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next com-
mand byte. EOC goes high when CS or CNVST go low.
EOC is always high in clock mode 11.
Single-Ended or Differential Conversions
The MAX1220/MAX1257/MAX1258 use a fully differen-
tial ADC for all conversions. When a pair of inputs are
connected as a differential pair, each input is connect-
ed to the ADC. When configured in single-ended mode,
the positive input is the single-ended channel and the
negative input is referred to AGND. See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
AIN14/AIN15. AIN0–AIN7 are available on all devices.
AIN0–AIN15 are available on the MAX1257/MAX1258.
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