DS33R41 Datasheet, PDF (248/333 Pages) Maxim Integrated Products – Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
TR.TLBC
Transmit Line Build-Out Control
7Dh
Bit #
7
Name
—
Default
0
6
AGCE
0
5
GC5
0
4
GC4
0
3
GC3
0
2
GC2
0
1
GC1
0
0
GC0
0
Bit 6: Automatic Gain Control Enable (AGCE)
0 = use Transmit AGC, TR.TLBC bits 0–5 are “don’t care”
1 = do not use Transmit AGC, TR.TLBC bits 0–5 set nominal level
Bits 5 to 0: Gain Control Bits (GC5 to GC0). The GC0 through GC5 bits control the gain setting automatic gain
control is disabled. Use the tables below for setting the recommended values. The LB (line build-out) column refers
to the value in the L0–L2 bits in TR.LIC1 (Line Interface Control 1) register.
NETWORK MODE
T1, Impedance Match Off
T1, Impedance Match On
E1, Impedance Match Off
E1, Impedance Match On
LB GC5 GC4 GC3 GC2 GC1 GC0
0
1
0
0
1
1
0
1
0
1
1
0
1
1
2
0
1
1
0
1
0
3
1
0
0
0
0
0
4
1
0
0
1
1
1
5
1
0
0
1
1
1
6
0
1
0
0
1
1
7
1
1
1
1
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
2
0
1
0
1
0
1
3
0
1
1
0
1
0
4
1
0
0
0
1
0
5
1
0
0
0
0
0
6
0
0
1
1
0
0
7
1
1
1
1
1
1
0
1
0
0
0
0
1
1
1
0
0
0
0
1
4
1
0
1
0
1
0
5
1
0
1
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
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