MAX1533A Datasheet, PDF (24/38 Pages) Maxim Integrated Products – High-Efficiency, 5x Output, Main Power-Supply Controllers for Notebook Computers

High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
When adjusting both output voltages, set the 3.3V
SMPS lower than the 5V SMPS. LDO5 connects to the
5V output (CSL5) through an internal switch only when
CSL5 is above the LDO5 bootstrap threshold (4.56V).
Similarly, LDO3 connects to the 3.3V output (CSL3)
through an internal switch only when CSL3 is above the
LDO3 bootstrap threshold (2.91V). Bootstrapping works
most effectively when the fixed output voltages are
used. Once LDO_ is bootstrapped from CSL_, the inter-
nal linear regulator turns off. This reduces internal
power dissipation and improves efficiency at higher
input voltage.
Current-Limit Protection (ILIM_)
The current-limit circuit uses differential current-sense
inputs (CSH_ and CSL_) to limit the peak inductor cur-
rent. If the magnitude of the current-sense signal
exceeds the current-limit threshold, the PWM controller
turns off the high-side MOSFET (Figure 3). At the next
rising edge of the internal oscillator, the PWM controller
does not initiate a new cycle unless the current-sense
signal drops below the current-limit threshold. The
actual maximum load current is less than the peak cur-
rent-limit threshold by an amount equal to half of the
inductor ripple current. Therefore, the maximum load
capability is a function of the current-sense resistance,
inductor value, switching frequency, and duty cycle
(V_OUT / V_IN).
In forced-PWM mode, the MAX1533A/MAX1537A also
implement a negative current limit to prevent excessive
reverse inductor currents when V_OUT is sinking current.
The negative current-limit threshold is set to approxi-
mately 120% of the positive current limit and tracks the
positive current limit when ILIM_ is adjusted.
Connect ILIM_ to V_CC for the 75mV default threshold, or
adjust the current-limit threshold with an external resis-
tor-divider at ILIM_. Use a 2µA to 20µA divider current
for accuracy and noise immunity. The current-limit
threshold adjustment range is from 50mV to 200mV. In
the adjustable mode, the current-limit threshold voltage
equals precisely 1/10th the voltage seen at ILIM_. The
logic threshold for switchover to the 75mV default value
is approximately V_CC - 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the dif-
ferential current-sense signals seen by CSH_ and
CSL_. Place the IC close to the sense resistor with
short, direct traces, making a Kelvin-sense connection
to the current-sense resistor.
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V_IN -
V_OUT differential exists. The high-side gate drivers
(DH_) source and sink 2A, and the low-side gate dri-
vers (DL_) source 1.7A and sink 3.3A. This ensures
robust gate drive for high-current applications. The
DH_ floating high-side MOSFET drivers are powered by
diode-capacitor charge pumps at BST_ (Figure 6) while
the DL_ synchronous-rectifier drivers are powered
directly by the fixed 5V linear regulator (LDO5).
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL_ and DH_ drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly;
otherwise, the sense circuitry in the MAX1533A/
MAX1537A interprets the MOSFET gates as “off” while
charge actually remains. Use very short, wide traces (50
to 100 mils wide if the MOSFET is 1 inch from the driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.6Ω (typ) on-resistance. This helps pre-
vent DL_ from being pulled up due to capacitive cou-
pling from the drain to the gate of the low-side
MOSFETs when the inductor node (LX_) quickly switch-
es from ground to V_IN. Applications with high input volt-
ages and long inductive driver traces may require
additional gate-to-source capacitance to ensure fast-
rising LX_ edges do not pull up the low-side MOSFETs’
gate, causing shoot-through currents. The capacitive
coupling between LX_ and DL_ created by the
MOSFET’s gate-to-drain capacitance (C_RSS), gate-to-
source capacitance (C_ISS - C_RSS), and additional
board parasitics should not exceed the following
minimum threshold:
V_GS(TH)
>
⎛
V_{IN⎝⎜}
C_RSS
C_ISS
⎞
⎠⎟
Lot-to-lot variation of the threshold voltage may cause
problems in marginal designs. Alternatively, adding a
resistor less than 10Ω in series with BST_ may remedy
the problem by increasing the turn-on time of the high-
side MOSFET without degrading the turn-off time
(Figure 6).
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