DS4830 Datasheet, PDF (24/29 Pages) Maxim Integrated Products – Optical Microcontroller 16-Bit MAXQ20 Low-Power Microcontroller

DS4830
Optical Microcontroller
Temperature Measurement
The device provides an internal temperature sensor for
die temperature monitoring and two external remote
temperature-sensing channels. In external temperature
mode, current is forced into an external diode that is con-
nected between user-specified channel pins. The diode
temperature is obtained by measuring the diode voltages
at multiple bias currents.
These temperature channels can be enabled independ-
ently by setting the appropriate bit locations in the
TEMPCN register. Whenever a temperature conversion
is complete, the corresponding flag (INTDAI for internal
conversion, EX0DAI and EX1DAI for external conversion)
is set. These can be configured to cause an interrupt,
and can be cleared by software. The temperature meas-
urement resolution is 0.0625NC.
The device can use all the three modes explained above
simultaneously by using a time-slicing mechanism per-
formed by the internal controller. The ADC-related SFRs
are accessed in module 1 and module 2. For details
about this and the three blocks, refer to the ADC section
of the DS4830 User’s Guide.
Fast Comparator/Quick Trips
The device supports 10-bit quick-trip comparison func-
tionality. The quick trips are required to continuously
monitor 5 to 14 channels in a round-robin sequence.
The quick- trip controller allows the user control of the list
of channels to monitor. Each mode has a corresponding
choice of list of channels for the round robin.
In any mode of quick-trip operation, the quick trip (ana-
log) performs two comparisons on any selected channel.
1) Comparison with a high-threshold value.
2) Comparison with a low-threshold value.
Any comparison above the high-threshold value or below
the low-threshold value causes a bit to set in the cor-
responding register. This bit can be used to trigger an
interrupt. The threshold values are stored in 32 internal
register (16 for low-threshold settings and 16 for high-
threshold settings). The quick-trip controller provides the
appropriate sequence of clock and threshold values for
the quick trips. Because the quick trips and the ADC use
the same input pins, the controller ensures that no colli-
sion takes place.
SMBus is a trademark of Intel Corp.
The quick-trip-related SFRs are accessed in module
5. Refer to the quick trip section of the DS4830 User’s
Guide for more information.
I²C-Compatible Interface Modules
The device provides two independent I²C-compatible
interfaces: one is a master and the other is a slave.
I²C-Compatible Master Interface
The device features an internal I²C-compatible master
interface for communication with a wide variety of exter-
nal I²C devices. The I²C-compatible master bus is a
bidirectional bus using two bus lines: the serial-data line
(MSDA) and the serial-clock line (MSCL). For the I²C-
compatible master, the device has ownership of the I²C
bus and drives the clock and generates the START and
STOP signals. This allows the device to send data to a
slave or receive data from a slave.
When the I²C-compatible master interface is disabled,
MSDA and MSCL can be used as GPIO pins P1.0 and
P1.1, respectively, and accessed through PO1/PI1/PD1.
I²C-Compatible Slave Interface
The device also features an internal I²C-compatible slave
interface for communication with a host. Furthermore,
the device can be in-system programmed (bootloaded)
through the I²C-compatible slave interface. T��h�e��t�w�o��i�n�t�e�r�-
face signals used by the I²C slave interface are SCL and
SDA. For the I²C-compatible slave interface, the device
relies on an externally generated clock to drive SCL and
responds to data and commands only when requested
by the I²C master device. The I²C-compatible slave inter-
face is open drain and requires external pullup resistors.
SMBus Timeout
Both the I²C-compatible master and slave interfaces can
work in SMBusK-compatible mode for communication
with other SMBus devices. To achieve this, a 30ms timer
has been implemented on the I²C-compatible slave inter-
face to make the interface SMBus compatible. The pur-
pose of this timer is to issue a timeout interrupt and thus
the firmware can reset the I²C-compatible slave interface
when the SCL is held low for longer than 30ms. The timer
only starts when none of the following conditions is true:
1) The I²C-compatible slave interface is in the idle state
and there is no communications on the bus.
2) The I²C-compatible slave interface is not working in
SMBus-compatible mode.
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