DS4830 Datasheet, PDF(21/29 Page) Maxim Integrated Products – Optical Microcontroller 16-Bit MAXQ20 Low-Power Microcontroller

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DS4830

Optical Microcontroller

All the registers that are cleared on POR are also cleared

on brownout reset.

Watchdog Timer Reset

The watchdog timer provides a mechanism to reset the

processor in the case of undesirable code execution. The

watchdog timer is a hardware timer designed to be peri-

odically reset by the application software. If the software

operates correctly, the timer is reset before it reaches its

maximum count. However, if undesirable code execution

prevents a reset of the watchdog timer, the timer reaches

its maximum count and resets the processor.

The watchdog timer is controlled through two bits in the

WDCN register (WDCN[5:4]: WD[1:0]). Its timeout period

can be set to one of the four programmable intervals

ranging from 212 to 221 system clock (MOSC) periods

(0.409ms to 0.210s). The watchdog interrupt occurs at

the end of this timeout period, which is 512 MOSC clock

periods, or approximately 50Fs, before the reset. The

reset generated by the watchdog timer lasts for four sys-

tem clock cycles, which is 0.4Fs. Software can determine

if a reset is caused by a watchdog timeout by checking

the watchdog timer reset flag (WTRF) in the WDCN reg-

ister. Execution resumes at location 8000h following a

watchdog timer reset.

External Reset

Asserting RST low causes the device to enter the reset

state. The external reset function is described in the

DS4830 Userâs Guide. Execution resumes at location

8000h after RST is released. The DAC and PWM outputs

are unchanged during execution of external reset.

Internal System Reset

The host can issue an I2C command (BBh) to reset the

communicating device. This reset has the same effect as

the external reset as far as the reset values of all registers

are concerned. Also, an internal system reset can occur

when the in-system programming is done (ROD = 1).

Further details are available in the DS4830 Userâs Guide.

Programmable Timer/Counter

The device features two general-purpose programmable

timer/counters. Various timing loops can be implemented

using the timers. Each general-purpose timer/counter

uses three SFRs. GTCN is the general control register,

GTV is the timer value register, and GTC is the timer

compare register.

The timer can be used in two modes: free-running mode

and compare mode with interrupts. Both are described in

detail in the DS4830 Userâs Guide.

The functionality of the timers can be accessed through

three SFRs for each of the general-purpose timers. The

timer and counter SFRs are accessed in module 0 and

module 3. Detailed information regarding the timer/coun-

ter block can be found in theDS4830 Userâs Guide.

Hardware Multiplier

The hardware multiplier (multiply-accumulate, or MAC

module) is a very powerful tool, especially for applica-

tions that require heavy calculations. This multiplier

can execute the multiply or multiply-negate, or multiply-

accumulate or multiply-subtract operation for signed or

unsigned operands in a single machine cycle. The MAC

module uses eight SFRs, mapped as register 0hâ05h

and 08hâ09h in module M3.

System Interrupts

Multiple interrupt sources are available to respond to

internal and external events. The MAXQ20 architecture

uses a single interrupt vector (IV) and single interrupt-

service routine (ISR) design. For maximum flexibility,

interrupts can be enabled globally, individually, or by

module. When an interrupt condition occurs, its indi-

vidual flag is set, even if the interrupt source is disabled

at the local, module, or global level. Interrupt flags must

be cleared within the firmware-interrupt routine to avoid

repeated interrupts from the same source. Application

software must ensure a delay between the write to the

flag and the RETI instruction to allow time for the inter-

rupt hardware to remove the internal interrupt condition.

Asynchronous interrupt flags require a one-instruction

delay and synchronous interrupt flags require a two-

instruction delay.

When an enabled interrupt is detected, execution jumps

to a user-programmable interrupt vector location. The IV

not changed to a different address, application firmware

must determine whether a jump to 0000h came from a

RST or interrupt source.

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