DS33Z44 Datasheet, PDF (23/181 Pages) Maxim Integrated Products – Quad Ethernet Mapper

NAME
A1/SCD
A2/X86ED
A3
A4
A5
A6
A7
A8
A9
D0/MOSI
D1/MISO
D2/SPICK
D3
D4
D5
DS33Z44 Quad Ethernet Mapper
PIN
TYPE
FUNCTION
Address Bit 1: Address bit 1 of the microprocessor interface.
SCD (Hardware Mode): Used in Hardware Mode to disable X⁴³+1 bit
B1
scrambling for both the transmit and receive paths. Applies to HDLC
and X.86 transport. When 1, X⁴³+1 scrambling is disabled. When 0,
X⁴³+1 scrambling is enabled. The software registers used for control
of this function are LI.RPPCL and LI.TPPCL.
Address Bit 2: Address bit 2 of the microprocessor interface.
X86ED (Hardware Mode): When in Hardware Mode, setting this pin
A2
high enables X.86 encapsulation for both the transmit and receive
data. When 0, HDLC encapsulation is used. The register used to
control this function in Software Mode is LI.TX86EDE.
B2
Address Bit 3: Address bit 3 of the microprocessor interface.
C2
Address Bit 4: Address bit 4 of the microprocessor interface.
A3
Address Bit 5: Address bit 5 of the microprocessor interface.
B3
Address Bit 6: Address bit 6 of the microprocessor interface.
C3
Address Bit 7: Address bit 7 of the microprocessor interface.
A4
Address Bit 8: Address bit 8 of the microprocessor interface.
B4
Address Bit 9: Address bit 9 of the microprocessor interface. Most
Significant Bit.
Data Bit 0: Bidirectional data bit 0 of the microprocessor interface.
Least Significant Bit. Not driven when CS = 1 or RST = 0.
A5
IOZ ^{Master Out Slave In (SPI Mode): Data stream that provides the}
instruction and address information to the external EEPROM when in
SPI Master Mode. MOSI is updated on the rising edge when CKPHA
is set high, and on the falling edge when set low.
Data Bit 1: Bidirectional data bit 1 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
A6
IOZ
Master In Slave Out (SPI Mode): Data path from the SPI EEPROM
to the DS33Z44. Must be synchronous with SPICK. The Serial
EEPROM SPI Interface will provide data to the DS33Z44, MSB first.
MISO is sampled on the falling edge when CKPHA is set high, and
on the rising edge when set low.
Data Bit 2: Bidirectional data bit 2 of the microprocessor interface.
A7
IOZ ^{Not driven when CS = 1 or RST = 0.}
SPICK: Provides clocking for SPI transactions.
B5
IOZ
Data Bit 3: Bidirectional data bit 3 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
B6
IOZ
Data Bit 4: Bidirectional data bit 4 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
B7
IOZ
Data Bit 5: Bidirectional data bit 5 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
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