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DS2174Q Datasheet, PDF (22/24 Pages) Maxim Integrated Products – EBERT
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6.2 Data Interface
Figure 6-3. Transmit Interface Timing
TCLK
TCLK_EN
TCLKO
t CYC
t PWH
t PWL
t SU
tH
t OD
t PWH(1)
t OD(1)
TDAT
DATA OUT
DS2174
GAPPED CLOCK
GAPPED CLOCK
Table 6-C. TRANSMIT DATA TIMING
(VDD = 3.0V to 3.6V, TA = 0°C to +70°C for DS2174Q; VDD = 3.0V to 3.6V, TA = -40°C to +85°C
for DS2174QN)
PARAMETER
TCLK Clock Period (Nibble/Byte Mode)
TCLK High Time (Nibble/Byte Mode)
TCLK Low Time (Nibble/Byte Mode)
TCLK Clock Period (Bit Mode)
TCLK High Time (Bit Mode)
TCLK Low Time (Bit Mode)
TCLK_EN Setup Time Before TCLK­
TCLK_EN Hold Time After TCLK­
TCLKO Output Delay After TCLK­
TCLKO High Time (Nibble/Byte Mode)
TCLKO High Time (Bit Mode)
TDAT Output Delay After TCLKO¯
SYMBOL
tCYC
tPWH
tPWL
tCYC
tPWH
tPWL
tSU
tH
tOD
tPWH(1)
tPWH(1)
tOD(1)
MIN
12.5
5.0
5.0
6.45
2.0
2.0
2.5
2.5
5.0
2.0
TYP
½ tCYC
½ tCYC
½ tCYC
½ tCYC
MAX
6.0
5.0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
3
3
3
1
1
1, 3
1, 2
NOTES:
1) 20pF load.
2) TDAT follows falling edge of TCLKO if CR4.5 = 0, rising edge if CR4.5 = 1.
3) Guaranteed by design.
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