DS2174Q Datasheet, PDF (18/24 Pages) Maxim Integrated Products – EBERT

4. RAM ACCESS
DS2174
4.1 Indirect Addressing
512 bytes of memory, which is addressed indirectly, are available for repetitive patterns. Data bytes are
loaded one at a time into the indirect address register at address 0Fh. The RAM mode control bit, CR4.3,
determines the access to the RAM. If CR4.3 = 0, the RAM is under control of the BERT state machine. If
CR4.3 = 1, the RAM is under the control of the parallel port. This section discusses CR4.3 = 1.
The accompanying flow chart describes the algorithm used to write repetitive patterns to the RAM. The
programmer initializes a counter (n) to -1 in software, then sets CR4.3 and clears CR4.4. The rising edge
of CR4.3 resets the RAM address pointer to address 00h. Address 0Fh becomes the indirect access port to
the RAM. A write cycle on the parallel port to address 0Fh writes to the address in RAM pointed to by
the address pointer. The end of the write cycle, rising edge of WR, increments the address pointer. The
programmer then increments the counter (n) by 1 and loops until the pattern load is complete. Clear
CR4.3 to return control of the RAM to the BERT state machine. Finally, write the value in the counter (n)
back to address 04h and 05h to mark the last address of the pattern in memory.
The RAM contents can be verified by executing the same algorithm, replacing the parallel-port write with
a read, and setting CR4.4. CR4.3 must remain set for the entire algorithm to properly increment the
address pointer.
START
CR4.3=1
CR4.4=0
n = -1
WRITE BYTE TO ADDRESS
0Fh
n=n+1
NO
LAST BYTE?
YES
WRITE n TO CR3
IF n > 255, THEN
SET CR4.0
CR4.3 = 0
DONE
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