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MAX5950 Datasheet, PDF (21/28 Pages) Maxim Integrated Products – 12V PWM Controller with Hot-Swap
12V PWM Controller with Hot-Swap
quency is higher than fLC, but lower than the closed-
loop crossover frequency. The equations that define
the error amplifier’s poles and zeroes (fZ1, fZ2, fP1, fP2,
and fP3) are the same as before. However, fP2 is now
lower than the closed-loop crossover frequency. Figure
7 shows the error-amplifier feedback, as well as its gain
response for circuits that use higher ESR output capac-
itors (tantalum, aluminum electrolytic, etc.)
Pick a value for feedback resistor R5 in Figure 7 (values
between 1kΩ and 10kΩ are adequate). C7 is then cal-
culated as:
C7 =
1
2π × 0.5 × fLC × R5
The circuit is implemented with C7 >> C8 and R3 >>
R6, in which case the error-amplifier gain between fP2
and fP3 is approximately equal to:
R5
R6
The modulator gain at fC is:
GMOD(fC)
=
(2π)2
GMOD(DC)
× L × COUT
×
fC2
Since GEA(fC) x GMOD(fC) = 1, R6 can then be calculat-
ed as:
R6 ≈
R5 × GMOD(DC)
(2π)2 × L × COUT ×
fC2
fP2 is set to fZESR. C6 is then calculated as:
C6 = COUT × ESR
R6
R3 is then calculated as:
R3 ≈
1
2π × fLC × C6
fP3 is set at 5xfC. Therefore, C8 is calculated as:
C8 =
1
2π × R5 × 5 × fC
Hot-Swap Controller
Applications Information
Additional External Gate Capacitance
External capacitance can be added from the gate of the
external MOSFET to AGND to reduce the dv/dt of the
PWM controller input voltage (VPWM_IN), decreasing the
hot-swap inrush current. Add a 10kΩ resistor in series
with the added gate capacitor to prevent degrading the
device turn-off response to a fault condition.
Layout Considerations
To take advantage of the switch response time to an
output fault condition, it is important to keep all traces as
short as possible and to maximize the high-current trace
width to reduce the effect of undesirable parasitic
inductance. Use a ground plane to minimize impedance
and inductance. Minimize the trace length that connects
to IN and HSENSE (< 10mm), and ensures accurate
current sensing with Kelvin connections.
When the output is short circuited, the voltage drop
across the external MOSFET becomes large. Hence,
the power dissipation in the switch increases, as does
the die temperature. An efficient way to achieve good
power dissipation on a surface-mount package is to lay
out two copper pads directly under the MOSFET pack-
age on both sides of the board. Connect the two pads
to the ground plane through vias, and use enlarged
copper mounting pads on the top side of the board.
PWM Controller
Applications Information
Power Dissipation
The 32-pin TQFN thermally enhanced package can dis-
sipate 2.7W. Calculate power dissipation in the
MAX5950 as a product of the input voltage and the
total REG output current (IREG). IREG includes quies-
cent current (IQ) and gate-drive current (IDREG):
PD = VIN x IREG
IREG = IQ + [fSW x (QG1 + QG2)]
where QG1 and QG2 represent the total gate charge of
the low-side and high-side external MOSFETs, fSW is the
switching frequency of the converter, and IQ is the quies-
cent current of the device at the switching frequency.
Use the following equation to calculate the maximum
power dissipation (PDMAX) in the chip at a given ambi-
ent temperature (TA):
PDMAX = 34.5 x (150 - TA)……….mW
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