MAX15023_11 Datasheet, PDF (21/28 Pages) Maxim Integrated Products – Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller

Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
Type III Compensation Network
(See Figure 5)
If the output capacitor used is a low-ESR tantalum or
ceramic type, the ESR-induced zero frequency is usual-
ly above the targeted zero crossover frequency (f_O). In
this case, Type III compensation is recommended.
Type III compensation provides three poles and two
zeros at the following frequencies:
f_Z1
=
2π
×
1
R_F
× C_F
f_Z2
=
2π
× C_I
1
× (R₁ + R_I)
Two midband zeros (f_Z1 and f_Z2) cancel the pair of
complex poles introduced by the LC filter:
f_P1 = 0
f_P1 introduces a pole at zero frequency (integrator) for
nulling DC output voltage errors:
f_P2
=
2π
×
1
R_I
×
C_I
Depending on the location of the ESR zero (f_ZO), f_P2
can be used to cancel it, or to provide additional atten-
uation of the high-frequency output ripple:
f_P3
=
2π
× R_F
1
× ^CF
C_F
×
+
C_CF
C_CF
f_P3 attenuates the high-frequency output ripple.
The locations of the zeros and poles should be such
that the phase margin peaks around f_O.
Ensure that R_F>>2/g_m (1/g_m(MIN) = 1/600µS = 1.67kΩ)
and the parallel resistance of R₁, R₂, and R_I is greater
than 1/g_m. Otherwise, a 180° phase shift is introduced
to the response and will make it unstable.
The following procedure is recommended:
1) With R_F ≥ 10kΩ, place the first zero (f_Z1) at 0.5 x
f_PO:
f_Z1 =
1
2π × R_F
× C_F
= 0.5 × f_PO
so:
C_F
=
2π
× R_F
1
× 0.5 ×
f_PO
2) The gain of the modulator (Gain_MOD)—composed of
the regulator’s pulse-width modulator, LC filter,
feedback divider, and associated circuitry at
crossover frequency is:
Gain_MOD
=
V_IN
V_OSC
×
(2π
×
f_O)²
1
× L_OUT
× C_OUT
The gain of the error amplifier (Gain_EA) in midband fre-
quencies is:
Gain_EA = 2π × f_O × C_I × R_F
The total loop gain as the product of the modulator gain
and the error amplifier gain at f_O should be equal to 1.
So:
Therefore:
Gain_MOD × Gain_EA = 1
V_IN
V_OSC
×
(2π
×
f_O)²
×
1
C_OUT
× L_OUT
× 2π × f_O × C_I × R_F = 1
Solving for C_I:
( ) _CI
=
V_OSC ×
2π × f_O × L_OUT
V_IN × R_F
× C_OUT
3) If f_PO < f_O < f_ZO < f_SW/2, the second pole (f_P2)
should be used to cancel f_ZO. This way, the Bode
plot of the loop gain plot does not flatten out soon
after the 0dB crossover, and maintains its
-20dB/decade slope up to 1/2 the switching frequen-
cy. This is likely to occur if the output capacitor is a
low-ESR tantalum or polymer. Then set:
f_P2 = f_ZO
If a ceramic capacitor is used, then the capacitor ESR
zero, f_ZO, is likely to be located even above 1/2 the
switching frequency, that is, f_PO < f_O< f_SW/2 < f_ZO. In
this case, the frequency of the second pole (f_P2) should
be placed high enough in order not to significantly
erode the phase margin at the crossover frequency. For
example, it can be set at 5 x f_O, so that its contribution
to phase loss at the crossover frequency, f_O, is only
about 11°:
f_P2 = 5 x f_O
Once f_P2 is known, calculate R_I:
R_I
=
2π
×
1
f_P2
×
C_I
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