MAX15023_11 Datasheet, PDF (20/28 Pages) Maxim Integrated Products – Wide 4.5V to 28V Input, Dual-Output Synchronous Buck Controller

Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
It is recommended to have a phase margin around
+50° to +60° to maintain a robust loop stability and
well-behaved transient response.
If an electrolytic or large-ESR tantalum output capacitor
is used, the capacitor ESR zero f_ZO typically occurs
between the LC poles and the crossover frequency f_O
(f_PO < f_ZO < f_O). In this case, use a Type II (PI or pro-
portional-integral) compensation network.
If a ceramic or low-ESR tantalum output capacitor is
used, the capacitor ESR zero typically occurs above
the desired crossover frequency f_O, that is f_PO < f_O <
f_ZO. In this situation, choose a Type III (PID or propor-
tional-integral-derivative) compensation network.
Type II Compensation Network
(See Figure 4)
If f_ZO is lower than f_O and close to f_PO, the phase lead
of the capacitor ESR zero almost cancels the phase
loss of one of the complex poles of the LC filter around
the crossover frequency. Therefore, a Type II compen-
sation network with a midband zero and a high-fre-
quency pole can be used to stabilize the loop. In Figure
4, R_F and C_F introduce a midband zero (f_Z1). R_F and
C_CF in the Type II compensation network also provide a
high-frequency pole (f_P1), which mitigates the effects of
the output high-frequency ripple.
To calculate the component values for Type II compen-
sation network in Figure 4, follow the instruction below:
1) Calculate the gain of the modulator (Gain_MOD)—
composed of the regulator’s pulse-width modulator,
LC filter, feedback divider, and associated circuitry
at crossover frequency:
( ) ^GainMOD
= ^VIN ×
V_OSC
ESR
2π × f_O × L_OUT
× ^VFB
V_OUT
where V_IN is the regulator’s input voltage, V_OSC is the
amplitude of the ramp in the pulse-width modulator,
V_FB is the FB_ input voltage set-point (0.6V typically,
see Electrical Characteristics table), and V_OUT is the
desired output voltage.
The gain of the error amplifier (Gain_EA) in midband fre-
quencies is:
Gain_EA = g_m × R_F
where g_m is the transconductance of the error amplifier.
The total loop gain as the product of the modulator gain
and the error amplifier gain at f_O should equal 1. So:
Gain_MOD × Gain_EA = 1
Therefore:
V_IN
V_OSC
×
ESR
(2π × f_O × L_OUT)
×
V_FB
V_OUT
× g_m
× R_F
=1
Solving for R_F:
( ) _RF
=
V_OSC × 2π × f_O × L_OUT × V_OUT
V_FB × V_IN × g_m × ESR
2) Set a midband zero (f_Z1) at 0.75 x f_PO (to cancel
one of the LC poles):
f_Z1 =
1
2π × R_F
× C_F
= 0.75 × f_PO
Solving for C_F:
C_F
=
2π
× R_F
1
× f_PO
× 0.75
3) Place a high-frequency pole at f_P1 = 0.5 x f_SW (to
attenuate the ripple at the switching frequency, f_SW)
and calculate C_CF using the following equation:
C_CF
=
π × R_F
1
× f_SW
−
1
C_F
VOUT
R1
R2
VREF
gm
RF
CF
COMP
CCF
Figure 4. Type II Compensation Network
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