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MAX1471_10 Datasheet, PDF (20/26 Pages) Maxim Integrated Products – 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 5. Register Configuration
ADDRESS
A3 A2 A1 A0
POWER CONFIGURATION (0x0)
0000
CONFIGURATION (0x1)
0001
CONTROL (0x2)
0010
OSCILLATOR FREQUENCY (0x3)
0011
OFF TIMER (upper byte) (0x4)
0100
OFF TIMER (lower byte) (0x5)
0101
CPU RECOVERY TIMER (0x6)
0110
RF SETTLE TIMER (upper byte) (0x7)
0111
RF SETTLE TIMER (lower byte) (0x8)
1000
STATUS REGISTER (read only) (0x9)
D7
LNA_EN
X
X
d7
t15
t7
t7
t15
t7
D6
D5
AGC_EN MIXER_
EN
GAIN FSKCALL
SET*
SB
AGC
LOCK
X
d6
d5
t14
t13
t6
t5
t6
t5
t14
t13
t6
t5
DATA
D4
D3
D2
D1
FSKBB_ FSKPD_ ASKBB_ ASKPD_
EN
EN
EN
EN
FSK_
DOUT
ASK_
DOUT
TOFF_
PS1
TOFF_
PS0
X
FSKTRK_ ASKTRK_ POL_
EN
EN
C AL_E N
d4
d3
d2
d1
t12
t11
t10
t9
t4
t3
t2
t1
t4
t3
t2
t1
t12
t11
t10
t9
t4
t3
t2
t1
D0
SLEEP
DRX_
MODE
FSK_CAL
_EN
d0
t8
t0
t0
t8
t0
1001
AGC DWELL TIMER (0xA)
1010
LOCK AGCST
CLK
X
DET
ALIVE
X
X
X
dt4
X
X
POL_CAL FSK_CAL
_DONE _DONE
dt3*
dt2*
dt1
dt0*
*Power-up state = 1. All other bits, power-up state = 0.
During tOFF, the MAX1471 is operating with very low
supply current (5.0µA typ), where all of its modules are
turned off, except for the tOFF timer itself. Upon com-
pletion of the tOFF time, the MAX1471 signals the user
by asserting DIO low.
CPU Recovery Timer (tCPU)
The second timer, tCPU (see Figure 12), is used to delay
the power-up of the MAX1471, thereby providing extra
power savings and giving a CPU the time required to
complete its own power-on sequence. The CPU is sig-
naled to begin powering up when the DIO line is pulled
low by the MAX1471 at the end of tOFF. tCPU then begins
counting down, while DIO is held low by the MAX1471.
At the end of tCPU, the tRF counter begins.
tCPU is an 8-bit timer, configured through register 0x6.
The possible tCPU settings are summarized in Table 11.
The data written to the tCPU register (0x6) is multiplied
by 120µs to give the total tCPU time. On power-up, the
CPU timer register is set to zero and must be written
before using DRX mode.
RF Settle Timer (tRF)
The third timer, tRF (see Figure 12), is used to allow the
RF sections of the MAX1471 to power up and stabilize
before ASK or FSK data is received. tRF begins count-
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