MAX1471_10 Datasheet, PDF (15/26 Pages) Maxim Integrated Products – 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
MAX1471
DATA ^{MAXIMUM PEAK}
SLICER
DETECTOR
MINIMUM PEAK
DETECTOR
ADATA
FDATA
PDMAXA
PDMAXF
R
C
PDMINA
PDMINF
R
C
Figure 5. Generating Data-Slicer Threshold Using the Peak Detectors
BASEBAND
FILTER
MINIMUM PEAK
DETECTOR
PDMINA
PDMINF
TRK_EN = 1
MAXIMUM PEAK
DETECTOR
PDMAXA
PDMAXF
TO SLICER
INPUT
MAX1471
TRK_EN = 1
Figure 6. Peak-Detector Track Enable
nect AVDD and DVDD together. In both cases, bypass
DVDD and HVIN with a 0.01µF capacitor and AVDD
with a 0.1µF capacitor. Place all bypass capacitors as
close as possible to the respective supply pin.
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