MAX1253 Datasheet, PDF(20/29 Page) Maxim Integrated Products – Stand-Alone, 10-Channel, 12-Bit System Monitors with Internal Temperature Sensor and VDD Monitor

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MAX1253 Datasheet, PDF (20/29 Pages) Maxim Integrated Products – Stand-Alone, 10-Channel, 12-Bit System Monitors with Internal Temperature Sensor and VDD Monitor

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Stand-Alone, 10-Channel, 12-Bit System Monitors

with Internal Temperature Sensor and VDD Monitor

Setup Register: Scan Mode Bit (B2)

The scan mode bit selects between automatic scan-

ning and manual conversion mode.

When set (B2 = 1), the MAX1253/MAX1254 enter auto-

matic scanning mode and convert every enabled chan-

nel starting with the internal temperature sensor,

followed by the VDD monitor, then sequencing through

AIN0 to AIN7.

After converting all the enabled channels, the

MAX1253/MAX1254 enter a wait state set by the sam-

ple wait bits in the setup register. After completing the

sample wait time, the scan cycle repeats.

When B2 = 0, the MAX1253/MAX1254 are in manual

mode and convert only the selected channel after

receiving a Manually Triggered Conversion command

(see the Manually Triggered Conversion (Command

Code 0000) section). Whether in automatic scanning

mode or manual mode, a Read Current Data Register

for Selected Channel command outputs the last-com-

pleted conversion result for the addressed channel at

DOUT.

Table 10. Reference Selection

B1 B0

REFERENCE MODE

Voltage measurements use external reference,

while temperature measurements use the internal

reference. A 20Âµs reference startup delay is

added prior to each temperature measurement

in this mode. This is the default mode after

power-up and after a software RESET.

All measurements use the internal reference. A

40Âµs reference startup delay is added prior to

starting the scanning of enabled channels,

0 1 allowing the internal reference to stabilize.

Note: For sample wait times less than 80Âµs, the

reference is continuously powered when in

automatic scan mode.

All measurements use the internal reference. By

selecting this mode, the reference is powered up

1 0 immediately when CS goes high after writing this

configuration. Once the reference system is

powered up, no further delay is added.

1 1 Reserved.

Table 11. Alarm Register Format

Setup Register: Reference Selection Bits (B1, B0)

The MAX1253/MAX1254 can be used with an internal

or external reference. Select between internal and

external reference modes through bits B1 and B0 of the

setup register (see Table 10).

Alarm Register

The alarm register (Table 11) holds the current alarm sta-

tus for all of the monitored signals. This 24-bit register

can only be read and cleared. The alarm register has 2

bits for each external input channel, 2 for the onboard

temperature sensor, and 2 for the VDD monitor (see

Table 12). At power-up, these bits are logic low, indicat-

ing no alarms at any input. When any bit in the alarm reg-

ister is set, INT becomes active and remains active until

all alarm bits are cleared. After a fault counter exceeds

the set threshold, the alarm register bits for that particular

channel are updated to indicate an alarm.

To clear the interrupt, reset the active alarm bit with the

Clear Alarm Register command, Clear Channel Alarm

command, a RESET command, or by writing a new

configuration to the faulting channel. The alarm register

defaults to 000000 hex.

Table 11 illustrates how the alarm register stores the

information on which channel a fault has occurred. The

alarm code for each bit pair is shown in Table 12.

Channel Registers

Each channel (internal temperature sensor, VDD moni-

tor, and AIN0 to AIN7) has registers to hold the conver-

sion result (current data register) and channel-specific

configuration data. The channel-specific configuration

registers include: the upper threshold register, the

lower threshold register, and the channel configuration

even channel of the differential input pair are used. The

channel-specific configuration registers for the odd

channel of a differential channel pair are ignored.

Table 12. Alarm Register Coding

(2 Bits/Channel)

CODE

DESCRIPTION

No alarm (power-up state)

Input is below lower threshold

Input is above upper threshold

Reserved

B23/B22 B21/B20 B19/B18 B17/B16 B15/B14 B13/B12 B11/B10 B9/B8

TEMP

VDD

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

B7/B6

AIN6

B5/B4

AIN7

B3/B2

Res

B1/B0

Res

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