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MAX16126 Datasheet, PDF (2/19 Pages) Maxim Integrated Products – Load-Dump/Reverse-Voltage Protection Circuits
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MAX16126/MAX16127
Load-Dump/Reverse-Voltage Protection Circuits
ABSOLUTE MAXIMUM RATINGS
(All pins referenced to GND.)
IN.............................................................................-30V to +90V
SHDN.............................................-0.3V to max (0V, VIN + 0.3V)
TERM.............................................-0.3V to max (0V, VIN + 0.3V)
SRC, GATE..............................................................-30V to +45V
SRC to GATE...........................................................-30V to +30V
OUT........................................................................-0.3V to +45V
FLAG......................................................................-0.3V to +45V
OVSET, UVSET.........................................................-0.3V to +6V
Continuous Sink/Source (all pins).................................. Q100mA
Continuous Power Dissipation (TA = +70NC) (multilayer board)
TQFN (derate 14.7mW/NC above +70NC)...............1176.5mW
Operating Temperature Range......................... -40NC to +125NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................. -60NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (BJA)...........68NC/W
Junction-to-Case Thermal Resistance (BJC)................11NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VIN = 12V, CGATE-SOURCE = 1nF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
Input Voltage Range
Input Supply Current
SRC Input Current
IN Undervoltage Lockout
OVSET/UVSET Input Current
OVSET/UVSET Threshold (Rising)
OVSET/UVSET Threshold Hysteresis
POK Threshold Rising
POK Threshold Falling
TERM On-Resistance
Startup Response Time
Autoretry Timeout
GATE Rise Time
OVSET to GATE Propagation Delay
SYMBOL
CONDITIONS
Operating range
VIN
Protection range
SHDN = high
IIN
SHDN = low
ISRC
VUVLO
VIN rising
IUVSET/OVSET
VTH
VIN rising
VTH-HYS
VPOK+
VPOK-
RTERM
tSTART
(Note 3)
tRETRY
tRISE
VGATE rising (GND to VSRC + 6V)
tOVG
VOVSET rising (VTH - 100mV to
VTH + 100mV)
MIN
TYP MAX
3
24
-30
+90
224
320
34
50
75
110
2.8
500
1.2 1.225 1.25
5
0.9 x VIN
0.87 x VIN
0.7
1.2
150
150
1
UNITS
V
FA
FA
V
nA
V
%
V
V
kI
Fs
ms
ms
0.55
Fs
UVSET to GATE Propagation Delay
tUVG
VUVSET rising (VTH - 100mV to
VTH +100mV)
20
Fs
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