MAX1636 Datasheet, PDF (19/24 Pages) Maxim Integrated Products – Low-Voltage, Precision Step-Down Controller for Portable CPU Power

Low-Voltage, Precision Step-Down
Controller for Portable CPU Power
determined by the input voltage and load current, with
the worst case occurring at V_IN = 2 x V_OUT:
( ) ^IRMS ^{= I}LOAD ^{× V}OUT ^VIN ^{− V}OUT ^{/ V}IN
Therefore, when V_IN is 2 x V_OUT:
I_RMS = I_LOAD / 2
Output Filter Capacitor Value
The output filter capacitor values are generally deter-
mined by the ESR and voltage-rating requirements
rather than actual capacitance requirements for loop
stability. In other words, the low-ESR electrolytic capac-
itor that meets the ESR requirement usually has more
output capacitance than is required for AC stability.
Use only specialized low-ESR capacitors intended for
switching-regulator applications, such as AVX TPS,
Sprague 595D, Sanyo OS-CON, or Nichicon PL series.
To ensure stability, the capacitor must meet both mini-
mum capacitance and maximum ESR values as given
in the following equations:
C_OUT > V_REF(1 + V_OUT / V_IN(MIN)) / V_OUT x R_SENSE x f
R_ESR < R_SENSE x V_OUT / V_REF
where R_ESR can be multiplied by 1.5, as discussed
below.
These equations are worst case, with 45 degrees of
phase margin to ensure jitter-free, fixed-frequency
operation, and provide a nicely damped output
response for zero to full-load step changes. Some cost-
conscious designers may wish to bend these rules with
less-expensive capacitors, particularly if the load lacks
large step changes. This practice is tolerable if some
bench testing over temperature is done to verify
acceptable noise and transient response.
No well-defined boundary exists between stable and
unstable operation. As phase margin is reduced, the
first symptom is timing jitter, which shows up as blurred
edges in the switching waveforms where the scope
does not quite sync up. Technically speaking, this jitter
(usually harmless) is unstable operation, since the duty
factor varies slightly. As capacitors with higher ESRs
are used, the jitter becomes more pronounced, and the
load-transient output voltage waveform starts looking
ragged at the edges. Eventually, the load-transient
waveform has enough ringing on it that the peak noise
levels exceed the allowable output voltage tolerance.
Note that even with zero phase margin and gross insta-
bility, the output voltage noise never gets much worse
than I_PEAK x R_ESR (under constant loads).
Designers of RF communicators or other noise-sensi-
tive analog equipment should be conservative and stay
within the guidelines. Designers of notebook computers
and similar commercial-temperature-range digital sys-
tems can multiply the R_ESR value by a factor of 1.5
without hurting stability or transient response.
The output voltage ripple, which is usually dominated
by the filter capacitor’s ESR, can be approximated as
I_RIPPLE x R_ESR. There is also a capacitive term, so the
full equation for ripple in continuous-conduction mode
is V_NOISE(p-p) = I_RIPPLE x [R_ESR + 1 / (2 x p x f x
C_OUT)]. In Idle Mode, the inductor current becomes
discontinuous, with high peaks and widely spaced
pulses, so the noise can actually be higher at light load
(compared to full load). In Idle Mode, calculate the out-
put ripple as follows:
V_{NOISE(p−p)}
=
0.02 x R_{ESR +}
R_SENSE
[ ^{( )}] ^{0.0003 x L x 1/V}OUT ^{+ 1/ V}IN ^{− V}OUT
( ) ^RSENSE ^{2 x C}F
Selecting Other Components
MOSFET Switches
The high-current N-channel MOSFETs must be logic-
level types with guaranteed on-resistance specifica-
tions at VGS = 4.5V. Lower gate-threshold
specifications are better (i.e., 2V max rather than 3V
max). Drain-source breakdown voltage ratings must at
least equal the maximum input voltage, preferably with
a 20% derating factor. The best MOSFETs have the
lowest on-resistance per nanocoulomb of gate charge.
Multiplying R_DS(ON) by Q_g provides a good figure of
merit for comparing various MOSFETs. Newer MOSFET
process technologies with dense cell structures gener-
ally perform best. The internal gate drivers tolerate
>100nC total gate charge, but 70nC is a more practical
upper limit to maintain best switching times.
In high-current applications, MOSFET package power
dissipation often becomes a dominant design factor.
I²R power losses are the greatest heat contributor for
both high-side and low-side MOSFETs. I²R losses are
distributed between Q1 and Q2 according to duty fac-
tor as shown in the equations below. Generally, switch-
ing losses affect only the upper MOSFET, since the
Schottky rectifier usually clamps the switching node
before the synchronous rectifier turns on. Gate-charge
losses are dissipated by the driver and do not heat the
MOSFET. Calculate the temperature rise according to
package thermal-resistance specifications to ensure
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