MAX16826_15 Datasheet, PDF (18/26 Pages) Maxim Integrated Products – Programmable, Four-String HB LED Driver with Output-Voltage Optimization and Fault Detection

MAX16826
Programmable, Four-String HB
LED Driver with Output-Voltage
Optimization and Fault Detection
I²C is an open-drain bus. Both SDA and SCL are bidi-
rectional lines, connected to a positive supply voltage
using a pullup resistor. They both have Schmitt triggers
and filter circuits to suppress noise spikes on the bus to
ensure proper device operation.
A bus master initiates communication with the
MAX16826 as a slave device by issuing a START con-
dition followed by the MAX16826 address. The
MAX16826 address byte consists of 7 address bits and
a read/write bit (R/W). After receiving the proper
address, the MAX16826 issues an acknowledge bit by
pulling SDA low during the ninth clock cycle.
START and STOP Conditions
Both SCL and SDA remain high when the bus is not
busy. The master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the MAX16826, it
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 4). Both START and STOP
conditions are generated by the bus master.
Bit Transfer
Each data bit, from the most significant bit to the least
significant bit, is transferred one by one during each
clock cycle. During data transfer, the SDA signal is
allowed to change only during the low period of the
SCL clock and it must remain stable during the high
period of the SCL clock (Figure 5).
Acknowledge
The acknowledge bit is used by the recipient to hand-
shake the receipt of each byte of data (Figure 6). After
data transfer, the master generates the acknowledge
clock pulse and the recipient pulls down the SDA line
during this acknowledge clock pulse, such that the
SDA line stays low during the high duration of the clock
pulse. When the master transmits the data to the
MAX16826, it releases the SDA line and the MAX16826
takes the control of SDA line and generates the
acknowledge bit. When SDA remains high during this
9th clock pulse, this is defined as the not acknowledge
signal. The master then generates either a STOP condi-
tion to abort the transfer, or a repeated START condi-
tion to start a new transfer.
SCL
SDA
START
CONDITION
(S)
Figure 5. Bit Transfer
START CONDITION
SCL
SDA
BY MASTER
S
SDA
BY SLAVE
Figure 6. Acknowledge
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DATA LINE STABLE
DATA VALID
DATA ALLOWED
TO CHANGE
CLOCK PULSE FOR ACKNOWLEDGMENT
1
2
8
STOP
CONDITION
(P)
9
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