MAX15058 Datasheet, PDF (18/21 Pages) Maxim Integrated Products – High-Efficiency, 3A, Current-Mode Synchronous, Step-Down Switching Regulator

High-Efficiency, 3A, Current-Mode
Synchronous, Step-Down Switching Regulator
R_C
=
R1+ R2
R2
×

1+
R_LOADK _S (1− D)
L × f_SW
−
0.5


g_MV × g_MC × R_LOAD
× 2πf_COC_OUT
×





^{ESR +}





1
R_LOAD
+
1

K
S
(1−
L×
D) −
f_SW
0.5

and where the ESR is much smaller than the parallel
combination of the equivalent load resistance and the
current loop impedance, e.g.,:
ESR <<
1
 _RLO1AD
+
K
S
(1−
L×
D) −
f_SW
0.5


RC becomes:
R_C
=
R1+ R2
R2
×
2πf_CO × C_OUT
g_MV × g_MC
3) Determine CC by selecting the desired first sys-
tem zero, fZ1, based on the desired phase margin.
Typically, setting fZ1 below 1/5 of fCO provides suf-
ficient phase margin.
f_Z1
=
2π
×
1
C _CR _C
≤
f_CO
5
therefore:
C_C
≥
2π
×
5
f_CO
×
R_C
4) For low duty-cycle applications, the addition of a
phase-leading capacitor (C_FF in Figure 1) helps
mitigate the phase lag of the damped half-frequency
double pole. Adding a second zero near to but below
the desired crossover frequency increases both the
closed-loop phase margin and the regulator’s unity-
gain bandwidth (crossover frequency). Select the
capacitor as follows:
C_FF
=
2π ×
1
f_CO ×
(R1|| R2)
Using CFF the zero-pole order is adjusted as follows:
f_P1
<
f_P2
≤
f_Z1
<
1_<
2πC_FFR1
1
2πC_FF (R1|| R2)
≈
f_CO < f_P3 < f_Z2
Confirm the desired operation of CFF empirically. The
phase lead of CFF diminishes as the output voltage
is a smaller multiple of the reference voltage, e.g.,
below about 1V. Do not use CFF when VOUT = VFB.
Setting the Soft-Start Time
The soft-start feature ramps up the output voltage slowly,
reducing input inrush current during startup. Size the
CSS capacitor to achieve the desired soft-start time, tSS,
using:
C _SS
=
I_SS × t _SS
V_FB
ISS, the soft-start current, is 10FA (typ) and VFB, the
output feedback voltage threshold, is 0.6V (typ). When
using large COUT capacitance values, the high-side
current limit can trigger during the soft-start period. To
ensure the correct soft-start time, tSS, choose CSS large
enough to satisfy:
C _SS
>>
C _OUT
×
V_OUT ×I_SS
(I_{HSCL_} − I_OUT ) ×
V_FB
I_{HSCL_} is the typical high-side MOSFET current-limit
value.
An external tracking reference with steady-state value
between 0V and V_IN - 1.8V can be applied to SS/REFIN.
In this case, connect an RC network from external track-
ing reference and SS/REFIN, as shown in Figure 4. The
recommended value for R_SS is approximately 1kI. R_SS
is needed to ensure that, during hiccup period, SS/
REFIN can be internally pulled down.
When an external reference is connected to SS/REFIN,
the soft-start must be provided externally.
VREF_EXT
RSS
CSS
SS/REFIN
MAX15058
This guarantees the additional phase-leading zero
occurs at a frequency lower than fCO from:
f_{PHASE_LEAD}
=
2π
×
1
C_FF
×
R1
Figure 4. RC Network for External Reference at SS/REFIN
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