MAX13325 Datasheet, PDF (18/21 Pages) Maxim Integrated Products – Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic

Dual Automotive, Audio Line Drivers
with I²C Control and Diagnostic
of an unsuccessful data transfer, the bus master may
retry communication. The master must pull down SDA
during the 9th clock cycle to acknowledge receipt of
data when the MAX13325/MAX13326 are in read mode.
An acknowledge must be sent by the master after each
read byte to allow data transfer to continue. A not-
acknowledge is sent when the master reads the final
byte of data from the MAX13325/MAX13326, followed by
a STOP condition.
Slave Address
The MAX13325/MAX13326 are programmable to one of
seven I²C slave addresses. These slave addresses are
unique device IDs. Connect ADD_ to GND, VL, SCL, or
SDA to set the I²C slave address. The address is defined
as the seven most significant bits (MSBs) followed by
the read/write bit. Set the read/write bit to 1 to configure
the MAX13325/MAX13326 to read mode. Set the read/
write bit to 0 to configure the device to write mode. The
address is the first byte of information sent after the
START condition.
Register Address Map
Single-Byte Write Operation
For a single-byte write operation, send the slave address
as the first byte followed by the register address and
then a single data byte (see Figure 5).
Burst Write Operation
For a burst write operation, send the slave address as
the first byte followed by the register address and then
the data bytes (see Figure 6).
Single-Byte Read Operation
For a single-byte read operation, send the slave address
with the read bit set, as the first byte followed by the reg-
ister address. Then send a Repeated START condition
followed by the slave address. After the slave sends the
data byte, send a not-acknowledge followed by a STOP
condition (see Figure 7).
Burst Read Operation
For a burst read operation, send the slave address with
a write as the first byte followed by the register address.
Then send a Repeated START condition followed by the
slave address. The slave sends data bytes until a not-
acknowledge condition is sent (see Figure 8).
S S7 S6 S5 S4 S3 S2 S1 ^R/W ACK C7 C6 C5 C4 C3 C2 C1 C0 ACK
=0
SLAVE ADDRESS
REGISTER ADDRESS
B7 B6 B5 B4 B3 B2 B1 B0 ACK P
DATA 1
Figure 5. A Single-Byte Write Operation
S S7 S6 S5 S4 S3 S2 S1 ^R/W ACK R7 R6 R5 R4 R3 R2 R1 R0 ACK
=0
SLAVE ADDRESS
REGISTER ADDRESS
B7 B6 B5 B4 B3 B2 B1 B0 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK
DATA 1
DATA 2
ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK P
DATA N
Figure 6. A Burst Write Operation
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