MAX13000E Datasheet, PDF (18/25 Pages) Maxim Integrated Products – Ultra-Low-Voltage Level Translators Enable/Shutdown Control

Ultra-Low-Voltage Level Translators
R_C 1MΩ R_D 1500Ω
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR RESISTANCE
HIGH-
VOLTAGE
DC
SOURCE
C_S
100pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
R_C
50Ω TO 100Ω
CHARGE-CURRENT-
LIMIT RESISTOR
R_D
330Ω
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
SOURCE
Cs
150pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 10. Human Body ESD Test Model
I_P 100%
90%
I_r
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
36.8%
10%
0
0 _tRL
TIME
t_DL
CURRENT WAVEFORM
Figure 11. Human Body Current Waveform
IEC 61000-4-2 Standard ESD Protection
The IEC 61000-4-2 standard (Figure 12) specifies ESD
tolerance for electronic systems. The IEC61000-4-2
model specifies a 150pF capacitor that is discharged
into the device through a 330Ω resistor. The
MAX13000E–MAX13005E’s I/O on the V_CC side are
rated for IEC 61000-4-2 standard, (8kV Contact
Discharge and ±10kV Air-Gap Discharge).
The IEC 61000-4-2 model discharges higher peak cur-
rent and more energy than the HBM due to the lower
series resistance and larger capacitor.
Applications Information
Power-Supply Decoupling
To reduce ripple and the chance of transmitting incor-
rect data, bypass V_L and V_CC to ground with a 0.1µF
capacitor. To ensure full ±15kV ESD protection, bypass
V_CC to ground with a 1µF capacitor. Place all capaci-
tors as close to the power-supply inputs as possible.
Figure 12. IEC 61000-4-2 Contact Discharge Test Model
UCSP Package Considerations
For general UCSP package information and PC layout
considerations, please refer to Maxim application note:
Wafer-Level Chip-Scale Package.
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
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