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MAX1667 Datasheet, PDF (16/28 Pages) Maxim Integrated Products – Chemistry-Independent, Level 2 Smart Battery Charger
Chemistry-Independent,
Level 2 Smart Battery Charger
Table 2a. Component Selection
DESIGNATION
MANUFACTURER
C1
Output Capacitor
C2, C7, C11
C3
C4, C5, C9, C10
AVX
Sprague
C6
Input Capacitor
C8
AVX
Sprague
D1, D4, D5
Schottky Diodes
D2, D3
Motorola
Central
NIEC
Central
L1
Inductor
M1
High-Side MOSFET
M2
Low-Side MOSFET
R1
Sense Resistor
R2, R4
R3
R5, R6
Sumida
Coiltronics
Coilcraft
IR
Fairchild
Motorola
Motorola
IRC
Dale
1A
3A
4A
68µF, 20V, low ESR
TPSE686M020R0150
594D686X0025R2T
0.1µF
47nF
1µF
2 x 22µF, 35V, low ESR
TPSE226M035R0200
594D226X0035R2T
22nF
1N5819 equivalent
1N5821 equivalent
1N5821 equivalent
MBRS130LT3
MBRS340T3
MBRS340T3
CMSH3-40
CMSH5-40
EC31
NSQ03A04
CMSH5-40
Schottky diode, 50mA IDC, 30V, CMPSH-3
33µH, 1A ISAT
33µH, 3A ISAT, 30V
33µH, 4A ISAT, 30V
CDH74-330
CDRH127-330
CDRH127-270
UP1B-330
UP3B-330
DS3316P-333
IRF7603
IRF7201
IRF7805
FDN359A
FDS4410
FDS6680
MTSF3N03HD
MMDF3N03HD
2N7002 equivalent
MMBF1170LT1
40mΩ ±1%, 1W
LR251201R040F
WSL-2512/0.04W/±1%
10kΩ ±5%, 1/16W
10kΩ ±1%, 1/16W
33Ω ±5%, 1/16W
_____________________Digital Section
SMBus Interface
The MAX1667 uses serial data to control its operation. The
serial interface complies with the SMBus specification (see
System Management Bus Specification, from the SBS
forum at www.sbs-Forum.org or from Intel Architecture
Labs: 800-253-3696). Charger functionality complies with
the Duracell/Intel Smart Charger Specification for a Level 2
charger.
The MAX1667 uses the SMBus Read-Word and Write-
Word protocols to communicate with the battery it is
charging, as well as with any host system that monitors
the battery to charger communications. The MAX1667
acts only as a slave device and never initiates communi-
cation on the bus; it receives commands and responds
to queries for status information. Figures 8a and 8b show
the SMBus Write-Word and Read-Word protocols.
Each communication with the MAX1667 begins with the
master issuing a START condition, which is a high-to-
low transition on SDA while SCL is high (Figure 1).
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