MAX15108 Datasheet, PDF (16/19 Pages) Maxim Integrated Products – High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator

High-Efficiency, 8A, Current-Mode
Synchronous Step-Down Switching Regulator
If COUT is large, or exhibits a lossy equivalent series
resistance (large ESR), the circuit’s second zero
might come into play around the crossover frequency
(fCO = ω/2G). In this case, a third pole can be induced
by a second (optional) small compensation capaci-
tor (CCC), connected from COMP to PGND. The loop
response’s fourth asymptote (in bold, Figure 4) is the
one of interest in establishing the desired crossover fre-
quency (and determining the compensation component
values). A lower crossover frequency provides for stable
closed-loop operation at the expense of a slower load
and line transient response. Increasing the crossover
frequency improves the transient response at the (poten-
tial) cost of system instability. A standard rule of thumb
sets the crossover frequency P 1/10th of the switching
frequency. First, select the passive and active power
components that meet the application’s requirements.
Then, choose the small-signal compensation compo-
nents to achieve the desired closed-loop frequency
response and phase margin as outlined in the Closing
the Loop: Designing the Compensation Circuitry section.
Closing the Loop:
Designing the Compensation Circuitry
Select the desired crossover frequency. Choose fCO
approximately 1/10th of the switching frequency fSW, or
fCO ≈ 100kHz.
Select RC using the transfer-loop’s fourth asymptote
gain (assuming fCO > fP1, fP2, and fZ1 and setting the
overall loop gain to unity) as follows:
1=
V_FB
V_OUT
× g_MV
×R_C
× G_MOD
× R_LOAD
×
1
2π × f_CO × C_OUT × (ESR + R_LOAD)
Therefore:
R_C
=
V_OUT
V_FB
×
2π
×
f_CO × C_OUT × (ESR + R_LOAD)
g_MV × G_MOD × R_LOAD
For RLOAD much greater than ESR, the equation can be
further simplified as follows:
R_C
=
V_OUT
V_FB
×
2π × f_CO × C_OUT
g_MV × G_MOD
where VFB is equal to 0.6V.
Determine CC by selecting the desired first system zero,
fZ1, based on the desired phase margin. Typically, set-
ting fZ1 below 1/5th of fCO provides sufficient phase
margin.
f_Z1 =
1
2π × C_CR_C
≤
f_CO
5
Therefore:
C_C
≥
2π
×
5
f_CO
×
R_C
If the ESR output zero is located at less than one-half
the switching frequency, use the (optional) secondary
compensation capacitor, CCC, to cancel it, as follows:
1
2π × C_CCR_C
=
f_P3
=
f_Z2
=
1
2π × C_OUTESR
therefore:
C _CC
=
C_OUT × ESR
R_C
If the ESR zero exceeds 1/2 the switching frequency,
use the following equation:
f_P3
=
2π ×
1
C _CCR _C
=
f_SW
2
Therefore:
C _CC
=
2π
×
2
f_SW
×
R_C
Overall CCC detracts from the overall system phase
margin. Place this third pole well beyond the desired
crossover frequency to minimize the interaction with the
system loop response at crossover. Ignore CCC in these
calculations if CCC is smaller than 10pF.
Power Dissipation
The IC is available in a 20-bump WLP package and can
dissipate up to 745.5mW at TA = +70NC. When the die
temperature exceeds +160NC, the thermal-shutdown
protection is activated. See the Thermal Shutdown
Protection section.
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