MAX15108 Datasheet, PDF (12/19 Pages) Maxim Integrated Products – High-Efficiency, 8A, Current-Mode Synchronous Step-Down Switching Regulator

High-Efficiency, 8A, Current-Mode
Synchronous Step-Down Switching Regulator
Applications Information
Setting the Output Voltage
Connect a voltage-divider (R1 and R2, see Figure 1)
from OUT to FB to PGND to set the DC-DC converter
output voltage. Choose R1 and R2 so that the DC errors
due to the FB input bias current do not affect the output-
voltage precision. With lower value resistors, the DC
error is reduced, but the amount of power consumed in
the resistive divider increases. A typical tradeoff value
for R2 is 5kI, but values between 1kI and 20kI are
acceptable. Once R2 is chosen, calculate R1 using:
R₁
=
R₂
×



V_OUT
V_FB

- 1_

where the feedback threshold voltage VFB = 0.6V.
Inductor Selection
A large inductor value results in reduced inductor ripple
current, leading to a reduced output ripple voltage. A
high-value inductor is of a larger physical size with a
higher series resistance (DCR) and a lower saturation
current rating. Choose inductor values to produce a
ripple current equal to 30% of the load current.
Choose the inductor with the following formula:
L
=
V_OUT
f_SW × ∆I_L
×

^1-

V_OUT
V_IN



where fSW is the internally fixed 1MHz switching fre-
quency, and DIL is the estimated inductor ripple current
(typically set to 0.3 x ILOAD). In addition, the peak induc-
tor current, IL_PK, must always be below the high-side
current-limit value, IHSCL, and the inductor saturation
current rating, IL_SAT.
Ensure that the following relationship is satisfied:
I_{L_PK}
= I_LOAD
+
1
2
× ∆I_L
<
MIN(I_HSCL ,I_{L_SAT} )
Input Capacitor Selection
For a step-down converter, the input capacitor CIN helps
to keep the DC input voltage steady, in spite of discon-
tinuous input AC current. Use low-ESR capacitors to
minimize the voltage ripple due to ESR.
Size CIN using the following formula:
C_IN
=
f_SW
×
I_LOAD
∆V_{IN_RIPPLE}
×
V_OUT
V_IN
FEEDBACK
DIVIDER
V_OUT
ERROR AMPLIFIER
POWER MODULATOR
COMPENSATION
RAMP
V_IN
OUTPUT FILTER
AND LOAD
R₁
FB
C
g_MC
COMP
CONTROL
R₂
LOGIC
PWM
COMPARATOR
g_MV
R_OUT
R_C
*C_CC
Q_HS
L_O
DCR
Q_LS
I_L
C_C
R_OUT = A_VEA/g_MV
REF
*C_CC IS OPTIONAL.
V_{COMP GMOD}
V_OUT
I_L
NOTE: THE G_MOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF
THE INDUCTOR INJECTED INTO THE OUTPUT LOAD. THIS REPRESENTS A
SIMPLIFICATION FOR THE POWER MODULATOR STAGE DRAWN ABOVE.
Figure 1. Peak Current-Mode Regulator Transfer Model
V_OUT
ESR
C_OUT
R_LOAD
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