MAX14691 Datasheet, PDF (16/19 Pages) Maxim Integrated Products – High-Accuracy, Adjustable Power Limiter

MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Calculate the maximum capacitive load (C_MAX) value that
can be connected to OUT using the following formula:
C_MAX(mF)
=
I_LIM(A)
^(MM−

x1)t_{×STt SI}(_Tm_{I(sm) s+)} t_+STtSOT(m_{O(sm) s)}
V_{IN_MAX}(V)

where M is the multiplier (1x/1.5x/2x) applied to the current
limit during startup. For example, when using MAX14691,
if V_{IN_MAX} = 30V, t_STO (min) = 1090ms, t_STI (min) = 22ms,
and I_LIM = 3A, C_MAX results in the theoretical maximum of
111mF. In this case, any capacitance larger than 111mF will
cause a fault condition because the capacitor cannot be
charged to a sufficient voltage before t_STO has expired. In
practical applications, the output capacitor size is limited by
the thermal performance of the PCB. Poor thermal design
can cause the thermal-foldback current-limiting function of
the device to kick in too early, which may further limit the
maximum capacitance that can be charged. Therefore,
good thermal PCB design is imperative to charge large
capacitor banks.
OUT Freewheeling Diode for Inductive Hard
Short to Ground
In applications with a highly inductive load, a freewheeling
diode is required between the OUT terminal and GND.
This protects the device from inductive kickback that
occurs during short-to-ground events.
PCB Layout Recommendations
To optimize the switch response to output short-circuit
conditions, it is important to reduce the effect of undesir-
able parasitic inductance by keeping all traces as short as
possible. Place input and output capacitors as close as
possible to the device (no more than 5mm). IN and OUT
must be connected with wide short traces to the power
bus. During steady-state operation, the power dissipation
is typically low and the package temperature change is
usually minimal.
PCB layout designs need to meet two challenges: high-
current input and output paths and important heat dis-
sipation.
Heat Dissipation
Maxim recommends the use of 2oz copper on FR4 isola-
tor in a four-layer configuration.
The layer stack needs to be Top (routing), GND (plane),
Power (plane, connected to V_OUT) and Bottom (routing),
in this order, from top to bottom.
Install the IC on an exposed pad landing of minimum
100 x 100 mils, with at least five through vias to the GND
plane. The vias should be 32mils in diameter, with a
16mils plated hole. The hole plating needs to be at least
0.5oz copper.
Provide a minimum of 1in x 1in area of copper plane on
all four layers. It is important to remember that the inner
planes do not contribute much to heat dissipation, due to
FR4 isolation, but are important from an electrical point
of view.
If possible, keep the top and bottom copper areas clear of
solder mask, as this will greatly improve heat dissipation.
Use a similarly large copper area connected directly to the
OUT pins. A dimension of 1in x 1in is also recommended.
This might look oversized for current path requirements,
but is essential for heat dissipation. Keep in mind that
heat is generated at the drain junction of the internal
nMOS pass FET, which is then eliminated through the
five OUT pins and needs to be dissipated on this same
copper area.
Current Path Requirements
Connect all five IN pins to a copper area that is at least
150mils wide. Using 2oz copper may reduce this require-
ment to 100mils. Remember to provide the same copper
trace width on the source connection, when using the
external pMOS pass FET (with the drain connected to the
IN pins).
Use extreme caution when placing the decoupling capaci-
tors to the IN and OUT pins. The tendency to go as close
as possible to the IC pins might interfere with the mini-
mum requirement of the trace width above.
It is important to note that the return load current does not
flow through the IC; therefore, it is important to provide an
external ground trace of at least the same width as the
input/output one.
Maxim recommends the use of a GND plane. Connect the
input and output grounds to this plane using at least four
plated vias each. The vias should be 84mils in diameter
(or 60mils x 60mils, if square), with a 35mils plated hole.
Additional Information
For more information on heat dissipation, see the IC
Application Section on http://www.maximintegrated.
com.
www.maximintegrated.com
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