MAX14521E_15 Datasheet, PDF (16/21 Pages) Maxim Integrated Products – Quad, High-Voltage EL Lamp Driver with I2C Interface

MAX14521E
Quad, High-Voltage EL Lamp Driver
with I²C Interface
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high are
control signals (see the START and STOP Conditions
section). SDA and SCL idle high when the I²C bus is not
busy.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
to the MAX14521E. The master terminates transmission
and frees the bus by issuing a STOP condition. The bus
remains active if a REPEATED START condition is gener-
ated instead of a STOP condition.
S
SCL
Sr
P
SDA
Figure 2. START, STOP, and REPEATED START Conditions
Early STOP Conditions
The MAX14521E recognizes a STOP condition at any
point during data transmission except if the STOP condi-
tion occurs in the same high pulse as a START condition.
For proper operation, do not send a STOP condition dur-
ing the same SCL high pulse as the START condition.
Slave Address
The MAX14521E has selectable device addresses
through external inputs. The slave address consists of
five fixed bits (B7–B3, set to 11110) followed by two pin
programmable bits (A1 and A0).
For example: If A1 and A0 are hardwired to ground, the
complete address is 1111000. The full address is defined
as the seven most significant bits followed by the read/
write bit. Set the read/write bit to 1 to configure the
MAX14521E to read mode. Set the read/write bit to 0 to
configure the MAX14521E to write mode. The address is
the first byte of information sent to the MAX14521E after
the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX14521E uses to handshake receipt each byte of
data when in write mode (see Figure 3). The MAX14521E
pull down SDA during the entire mastergenerated 9th
clock pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a receiv-
ing device is busy or if a system fault had occurred. In the
event of an unsuccessful data transfer, the bus master
may retry communication.
The master pulls down SDA during the 9th clock cycle to
acknowledge receipt of data when the MAX14521E are
in read mode. An acknowledge is sent by the master after
each read byte to allow data transfer to continue. A not
acknowledge is sent when the master reads the final byte
of data from the MAX14521E followed by a STOP condition.
START
CONDITION
SCL
1
2
CLOCK PULSE FOR
ACKNOWLEDGMENT
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 3. Acknowledge
Write Data Format
A write to the MAX14521E includes transmission of a
START condition, the slave address with the R/W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a STOP
condition. Figure 4 illustrates the proper frame format
for writing one byte of data to the MAX14521E. Figure 5
illustrates the frame format for writing n-bytes of data to
the MAX14521E.
The slave address with the R/W bit set to 0 indicates that
the master intends to write data to the MAX14521E. The
MAX14521E acknowledge receipt of the address byte
during the master-generated 9th SCL pulse.
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