MAX14521E_15 Datasheet, PDF (15/21 Pages) Maxim Integrated Products – Quad, High-Voltage EL Lamp Driver with I2C Interface

MAX14521E
Quad, High-Voltage EL Lamp Driver
with I²C Interface
Frequency Divider (AUXDIV1/AUXDIV0)
AUXDIV[1:0] sets the divisor to divide down the AUX input
frequency; see Table 12.
Audio Enable (AU4/AU3/AU2/AU1)
1 = Enable audio effect to EL output.
0 = Disable audio effect to EL output.
When FR_AM = 0 the EL outputs can be enabled and dis-
abled independently according to AU[4:1]. When FR_AM
= 1 then all AU[4:1] bits must be set to 1 (i.e. AU[4:1] =
1111) to enable the audio effect on the EL outputs.
EL Peak Ramping Time and EL Peak Voltage
Register (0x06, 0x07, 0x08, 0x09)
EL Ramping Time
(RT4_ _/RT3_ _/RT2_ _/RT1_ _)
RT_ _[2:0] sets the ramp time of each EL output; see
Table 14.
EL Peak-to-Peak Voltage
(EL1_ _/EL2_ _/EL3_ _/EL4_ _)
EL _ _[4:0] controls the peak-to-peak voltage of each EL
output. When EL _ _[4:0] = 00000, the EL output follows
Table 12. AUX Frequency Divider
Configuration
AUXDIV[1:0]
00
01
10
11
AUX FREQUENCY DIVIDER
16
8
4
2
COM. When EL_ _[4:0] = 11111, the EL output has a 150V
peak with respect to COM. The EL output voltage rises
linearly with EL_ _[4:0].
I²C Interface
The MAX14521E features an I²C-compatible as a slave
device, 2-wire serial interface consisting of a serial data
line (SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication to the device at clock rates up
to 400kHz. Figure 1 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. A master device writes data to the
MAX14521E by transmitting the proper slave address
followed by the register address and then the data word.
Each transmit sequence is framed by a START (S) or
REPEATED START (Sr) condition and a STOP (P) condi-
tion. Each word transmitted to the MAX14521E is 8 bits
long and is followed by an acknowledge clock pulse.
A master reading data from the MAX14521E transmits
data on SDA in sync with the master-generated SCL
pulses. The master acknowledges receipt of each byte
of data. Each read sequence is framed by a START or
REPEATED START condition, a not acknowledge, and a
STOP condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater than
500Ω, is required on SCL if there are multiple masters on
the bus, or if the master in a singlemaster system has an
open-drain SCL output. Series resistors in line with SDA
and SCL are optional. Series resistors protect the digital
inputs of the MAX14521E from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
Table 13. EL Output Configuration
REGISTER
0x04
0x07
0x08
0x09
B7
RT1_2
RT2_2
RT3_2
RT4_2
B6
RT1_1
RT2_1
RT3_1
RT4_1
B5
RT1_0
RT2_0
RT3_0
RT4_0
B4
EL1_4
EL2_4
EL3_4
EL4_4
B3
EL1_3
EL2_3
EL3_3
EL4_3
B2
EL1_2
EL2_2
EL3_2
EL4_2
B1
EL1_1
EL2_1
EL3_1
EL4_1
B0
EL1_0
EL2_0
EL3_0
EL4_0
Table 14. Ramping Time Configuration
RT_ _[2:0]
000
001
010
011
RAMPING TIME (MS)
< 0.1
62.5
125
250
RT_ _[2:0]
100
101
110
111
RAMPING TIME (MS)
500
750
1000
2000
www.maximintegrated.com
Maxim Integrated │  15