MAX1316 Datasheet, PDF (16/27 Pages) Maxim Integrated Products – 8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with 10V, 5V, and 0 to +5V Analog Input Ranges

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Table 2. Configuration Register
PART NO. STATE
MAX1316
ON
MAX1320
MAX1324
OFF
MAX1317
ON
MAX1321
MAX1325
OFF
MAX1318
ON
MAX1322
MAX1326
OFF
NA = Not applicable.
D0/CH0
1
0
1
0
1
0
D1/CH1
1
0
1
0
1
0
D2/CH2
1
0
1
0
NA
NA
BIT/CHANNEL
D3/CH3 D4/CH4
1
1
0
0
1
NA
0
NA
NA
NA
NA
NA
D5/CH5
1
0
NA
NA
NA
NA
D6/CH6
1
0
NA
NA
NA
NA
D7/CH7
1
0
NA
NA
NA
NA
To write to the configuration register, pull CS and WR
low, load bits D0–D7 onto the parallel bus, and force
WR high. The data are latched on the rising edge of
WR (Figure 4). It is possible to write to the configuration
register at any point during the conversion sequence;
however, it is not active until the next convert-start sig-
nal. At power-up, write to the configuration register to
select the active channels before beginning a conver-
sion. Shutdown does not change the configuration reg-
ister. See the Shutdown Mode and the ALLON sections
for information about using the configuration register for
power saving.
Starting a Conversion
To start a conversion using internal-clock mode, pull
CONVST low for at least the acquisition time (t₁). The
T/H acquires the signal while CONVST is low, and con-
version begins on the rising edge of CONVST. An end-
of-conversion signal (EOC) pulses low when the first
result becomes available, and for each subsequent
result until the end of the conversion cycle. The end-of-
last-conversion signal (EOLC) goes low when the last
conversion result is available (Figures 5, 6, and 7).
To start a conversion using external-clock mode, pull
CONVST low for at least the acquisition time (t₁). The T/H
acquires the signal while CONVST is low, and conversion
begins on the rising edge of CONVST. Apply an external
clock to CLK. To avoid T/H droop degrading the sampled
analog input signals, the first clock pulse should occur
within 10µs from the rising edge of CONVST, and have a
minimum clock frequency of 100kHz. The first conversion
result is available for read on the rising edge of the 17th
clock cycle, and subsequent conversions after every third
clock cycle thereafter (Figures 5, 6, and 7).
RD
t₂
CS
t₆
t₅
t₇
WR
t₁₄
D0–D7
t₁₅
DATA-IN
Figure 4. Write Timing
In both internal- and external-clock modes, CONVST
must be held high until the last conversion result is
read. For best operation, the rising edge of CONVST
must be a clean, high-speed, low-jitter digital signal.
Table 3 shows the total throughput as a function of the
clock frequency and the number of channels selected
for conversion. The calculations use the nominal speed
of the internal clock (10MHz) and a 200ns CONVST
pulse width.
16 ______________________________________________________________________________________