MAX1316 Datasheet, PDF (12/27 Pages) Maxim Integrated Products – 8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with 10V, 5V, and 0 to +5V Analog Input Ranges

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
MAX1316
MAX1320
MAX1324
41
42
43
44
45
46
47
48
—
PIN
MAX1317
MAX1321
MAX1325
41
42
43
44
45
46
47
48
9–12
Pin Description (continued)
MAX1318
MAX1322
MAX1326
41
42
43
44
45
46
47
48
7–12
NAME
FUNCTION
EOLC
RD
WR
CS
End-of-Last-Conversion Output. EOLC goes low to indicate the end
of the last conversion. EOLC returns high when CONVST goes low
for the next conversion sequence.
Read Input. When RD and CS go low, the device initiates a read
command of the parallel data buses, D0–D13. D0–D13 are high
impedance while either RD or CS is high.
Write Input. The write command initiates when WR and CS go low. A
write command loads the configuration byte on D0–D7.
Chip-Select Input. Pulling CS low activates the digital interface.
D0–D13 are high impedance while either CS or RD is high.
CONVST
Convert-Start Input. Driving CONVST high places the device in hold
mode and initiates the conversion process. The analog inputs are
sampled on the rising edge of CONVST. When CONVST is low, the
analog inputs are tracked.
CLK
SHDN
External-Clock Input. CLK accepts an external-clock signal up to
15MHz. Connect CLK to DGND for internally clocked conversions.
To select external-clock mode, set INTCLK/EXTCLK = 0.
Shutdown Input. Set SHDN = 0 for normal operation. Set SHDN = 1
for shutdown mode.
ALLON
I.C.
Enable-All-Channels Input. Drive ALLON high to enable all input
channels. When ALLON is low, only input channels selected as
active are powered. Select channels as active using the
configuration register.
Internally Connected. Connect I.C. to AGND. For factory use only.
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