MAX1276 Datasheet, PDF (16/18 Pages) Maxim Integrated Products – 1.8Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs with Internal Reference

1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
CNVST
SCLK
1
1
DOUT
0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
00
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
V_L
MAX1276 _SCLK
MAX1278
CNVST
DOUT
VDDINT
TCLK _{ADSP21_ _ _}
RCLK
TFS
RFS
DR
Figure 19. Interfacing to the ADSP21_ _ _
SUPPLIES
GND
V_L
10µF
0.1µF
10µF
0.1µF
V_DD
GND RGND
V_L
MAX1276
MAX1278
DGND V_L
DIGITAL
CIRCUITRY
Figure 20. Power-Supply Grounding Condition
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
sions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis-
ters should be configured for late framing (LAFR = 1)
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEN = 1001).
Connect the V_L pin to the ADSP21_ _ _ supply voltage
when the MAX1276/MAX1278 are operating with a sup-
ply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the V_DD power supply can
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1276/MAX1278 are mea-
sured using the end-points method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
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