DS1621 Datasheet, PDF (16/16 Pages) Dallas Semiconductor – Digital Thermometer and Thermostat

NOTES:
1. All voltages are referenced to ground.
DS1621
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V_DD is switched off.
3. I_CC specified with T_OUT pin open.
4. I_CC specified with V_CC at 5.0V and SDA, SCL = 5.0V, 0°C to 70°C.
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
V_{IH MIN} of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum t_HD:DAT has only to be met if the device does not stretch the LOW period (t_LOW) of the
SCL signal.
8. A fast mode device can be used in a standard mode system, but the requirement t_SU:DAT >250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t_RMAX + t_SU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
9. C_B —total capacitance of one bus line in pF.
10. Writing to the nonvolatile memory should only take place in the 0°C to 70°C temperature range.
TIMING DIAGRAM
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Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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