MAX16920 Datasheet, PDF (15/20 Pages) Maxim Integrated Products – Automotive Power-Management IC with Three Step-Down Converters and Linear Regulator

Automotive Power-Management IC with
Three Step-Down Converters and Linear Regulator
and:
D = ^VOUT
V_IN
where IOUT is the output current, D is the duty cycle,
and fSW is the switching frequency. Use additional input
capacitance at lower input voltages to avoid possible
undershoot below the UVLO threshold during transient
loading.
Output Capacitor Selection
The allowable output voltage ripple and the maximum
deviation of the output voltage during step load currents
determine the output capacitance and its ESR. The
output ripple is composed of ΔVQ (caused by the
capacitor discharge) and ΔVESR (caused by the ESR
of the output capacitor). Use low-ESR ceramic or alumi-
num electrolytic capacitors at the output. For aluminum
electrolytic capacitors, the entire output ripple is
contributed by ΔVESR. Use the ESROUT equation to cal-
culate the ESR requirement and choose the capacitor
accordingly. If using ceramic capacitors, assume
the contribution to the output ripple voltage from the
ESR and the capacitor discharge to be equal. The
following equations show the output capacitance and
ESR requirement for a specified output voltage ripple.
ESR = ΔVESR/ΔIP-P
COUT = ΔIP-P/(8 x ΔVQ x fSW)
where:
ΔI_P-P = (V_IN - V_OUT) x V_OUT/(V_IN x f_SW x L)
V_{OUT_RIPPLE} ~ ΔV_ESR + ΔV_Q
ΔIP-P is the peak-to-peak inductor current as calculated
above, and fSW is the converter’s switching frequency.
The allowable deviation of the output voltage during fast
transient loads also determines the output capacitance
and its ESR. The output capacitor supplies the load-
step current until the converter responds with a greater
duty cycle. The response time (tRESPONSE) depends on
the closed-loop bandwidth of the converter. The high
switching frequency of the MAX16920 allows for a higher
closed-loop bandwidth, thus reducing tRESPONSE and
the output capacitance requirement. The resistive drop
across the output capacitor’s ESR and the capacitor
discharge causes a voltage droop during a load step.
Use low-ESR ceramic capacitors for better transient
load and ripple/noise performance. Keep the maximum
output voltage deviations below the tolerable limits of
the electronics being powered. When using a ceramic
capacitor, assume an 80% and 20% contribution from
the output capacitance discharge and the ESR drop,
respectively. Use the following equations to calculate the
required ESR and capacitance value:
ESROUT = ΔVESR/ISTEP
COUT = (ISTEP x tRESPONSE)/ΔVQ
where ISTEP is the load step, and tRESPONSE is the
response time of the converter. The converter response
time depends on the control-loop bandwidth.
Electrolytic output capacitors can be used if a 2.2µF
ceramic capacitor is connected in parallel. At output
currents lower than the maximum, smaller capacitors
can be used. Use a 4.7µF or larger ceramic capacitor
on the output of the linear regulator, OUTA.
Setting the Output Voltage (DC-DC1,
DC-DC2, DC-DC3)
The output voltage for any of the DC-DC converters is
set by selecting resistor R1 according to the formula:
R1 = R2 x ((VOUT_ /1.22) - 1)
where V_{OUT_} is the desired output voltage, and R2 is the
value of the ground connected resistor (a good starting
value is 30kΩ). See Figure 2. When setting DC-DC1 or
DC-DC3 to output voltages higher than 3.3V, it is neces-
sary to add an additional resistive divider between the
converter output and the OUT1 or OUT3 pins. Resistor
values of 100kΩ and 50kΩ work well in all applications.
See Figure 3 for the exact configuration.
OUT_
R1
MAX16920
FB_
R2
GND
Figure 2. Setting the Output Voltage
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