MAX15112 Datasheet, PDF (15/23 Pages) Maxim Integrated Products – High-Efficiency, 12A, Current-Mode Synchronous Step-Down Regulator with Integrated Switches

MAX15112
High-Efficiency, 12A, Current-Mode Synchronous
Step-Down Regulator with Integrated Switches
Output Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output-ripple voltage,
and transient response of the DC-DC converter. The out-
put ripple occurs due to variations in the charge stored in
the output capacitor, the voltage drop due to the capaci-
tor’s ESR, and the voltage drop due to the capacitor’s
ESL. Estimate the output-voltage ripple due to the output
capacitance, ESR, and ESL as follows:
V_RIPPLE = V_RIPPLE(C) + V_RIPPLE(ESR) + V_RIPPLE(ESL)
where the output ripple due to output capacitance, ESR,
and ESL is:
V_RIPPLE(C)
=
8
×
∆I_P−P
C_OUT ×
f_SW
V_RIPPLE(ESR) = ∆I_P−P × ESR
and VRIPPLE(ESL) can be approximated as an inductive
divider from LX to GND:
V_RIPPLE
(ESL)
=
V_LX
×
ESL
L
=
V_IN
×
ESL
L
where VLX swings from VIN to GND.
The peak-to-peak inductor current (DIP-P) is:
∆I_P−P
=
(V_IN
−
V_OUT
)
×



L × f_SW
V_OUT
V_IN



When using ceramic capacitors, which generally have
low-ESR, DVRIPPLE(C) dominates. When using electro-
lytic capacitors, DVRIPPLE(ESR) dominates. Use ceramic
capacitors for low ESR and low ESL at the switching fre-
quency of the converter. The ripple voltage due to ESL is
negligible when using ceramic capacitors.
As a general rule, a smaller inductor-ripple current results
in less output-ripple voltage. Since inductor-ripple cur-
rent depends on the inductor value and input voltage, the
output-ripple voltage decreases with larger inductance
and increases with higher input voltages. However, the
inductor-ripple current also impacts transient-response
performance, especially at low VIN to VOUT differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter
capacitors by a sudden load step.
Load-transient response also depends on the selected
output capacitance. During a load transient, the output
instantly changes by ESR x ∆I_LOAD. Before the controller
can respond, the output deviates further, depending on
the inductor and output capacitor values. After a short
time, the controller responds by regulating the output
voltage back to the predetermined value.
Use higher C_OUT values for applications that require
light-load operation or transition between heavy load and
light load, triggering skip mode, causing output under-
shooting or overshooting. When applying the load, limit
the output undershooting by sizing C_OUT according to
the following formula:
C _OUT
=
∆I_LOAD
3f_CO × ∆V_OUT
where ∆IL_OAD is the total load change, f_CO is the unity-
gain bandwidth (or zero-crossing frequency), and ∆V_OUT
is the desired output undershooting. When removing the
load and entering skip mode, the device cannot control
output overshooting, since it has no sink current capabil-
ity; see the Skip Mode Frequency and Output Ripple
section to properly size C_OUT under this circumstance.
A worst-case analysis in sizing the minimum output
capacitance takes the total energy stored in the inductor
into account, as well as the allowable sag/soar (under-
shoot/overshoot) voltage as follows:
( ) ^{L × I2OUT}₍MAX₎ ^{− I2OUT}₍MIN₎
C_{OUT (MIN)} =
(V_FIN
+
V_SOAR )²
−
V
2
INIT
, voltage soar (overshoot)
( ) ^{L × I2OUT}₍MAX₎ ^{− I2OUT}₍MIN₎
C_OUT(MIN) =
V
2
INIT
−
(V_FIN
−
V_SAG ) ²
, voltage sag (undershoot)
where IOUT(MAX) and IOUT(MIN) are the initial and final
values of the load current during the worst-case load
dump, VINIT is the initial voltage prior to the transient,
VFIN is the steady-state voltage after the transient, VSOAR
is the allowed voltage soar (overshoot) above VFIN, and
VSAG is the allowable voltage sag below VFIN. The terms
(VFIN + VSOAR) and (VFIN - VSAG) represent the maxi-
mum/minimum transient output voltage reached during
the transient, respectively.
Use these equations for initial output-capacitor selection.
Determine final values by testing a prototype or an evalu-
ation circuit under the worst-case conditions.
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