MAX15039 Datasheet, PDF (15/18 Pages) Maxim Integrated Products – 6A, 2MHz Step-Down Regulator with Integrated Switches

6A, 2MHz Step-Down Regulator
with Integrated Switches
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the
inductor L and the output capacitor C_O. The ESR of the
output capacitor determines the zero. The double pole
and zero frequencies are given as follows:
f_{P1_LC} = f_{P2_LC} =
1
2π
x
L
x
C_O
x
⎛
⎝⎜
RR_OO++ERS_LR ⎞⎠⎟
f_{Z_ESR} = _2π
x
1
ESR
x
C_O
where R_L is equal to the sum of the output inductor’s DCR
(DC resistance) and the internal switch resistance,
R_DS(ON). A typical value for R_DS(ON) is 20mΩ (low-side
MOSFET) and 26mΩ (high-side MOSFET). R_O is the output
load resistance, which is equal to the rated output voltage
divided by the rated output current. ESR is the total equiv-
alent series resistance of the output capacitor. If there is
more than one output capacitor of the same type in paral-
lel, the value of the ESR in the above equation is equal to
that of the ESR of a single output capacitor divided by the
total number of output capacitors.
The high switching frequency range of the MAX15039
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer function zero is higher
than the unity-gain crossover frequency, fC, and the zero
cannot be used to compensate for the double pole creat-
ed by the output filtering inductor and capacitor. The dou-
ble pole produces a gain drop of 40dB/decade and a
phase shift of 180°. The compensation network error
amplifier must compensate for this gain drop and phase
shift to achieve a stable high-bandwidth closed-loop sys-
tem. Therefore, use type III compensation as shown in
Figures 3 and 4. Type III compensation possesses three
poles and two zeros with the first pole, f_{P1_EA}, located at
zero frequency (DC). Locations of other poles and zeros
of the type III compensation are given by:
f _{Z1_ EA}
=
2π
×
1
R1 ×
C1
f _{Z2 _ EA}
=
2π
×
1
R3
×
C3
f _{P3 _ EA}
=
2π
1
× R1 ×
C2
f _{P2 _ EA}
=
2π
×
1
R2
×
C3
The above equations are based on the assumptions
that C1 >> C2 and R3 >> R2, which are true in most
applications. Placements of these poles and zeros are
determined by the frequencies of the double pole and
ESR zero of the power transfer function. It is also a
function of the desired close-loop bandwidth. The fol-
lowing section outlines the step-by-step design proce-
dure to calculate the required compensation
components for the MAX15039. When the output volt-
age of the MAX15039 is programmed to a preset volt-
age, R3 is internal to the IC and R4 does not exist
(Figure 3b).
When externally programming the MAX15039 (Figure
3a), the output voltage is determined by:
R4
=
0.6 × R3
(V_OUT − 0.6)
(for
V_OUT
>
0.6V)
For a 0.6V output, connect an 8.06kΩ resistor from FB
to OUT. The zero-cross frequency of the close-loop, f_C,
should be between 10% and 20% of the switching fre-
quency, f_S. A higher zero-cross frequency results in
faster transient response. Once f_C is chosen, C1 is cal-
culated from the following equation:
2.5 x ^VIN
C1 =
2
x
π
x
R3
V_{P − P}
x (1+ ^RL ) ×
R_O
f_C
where V_P-P is the ramp peak-to-peak voltage (1V typ).
Due to the underdamped nature of the output LC dou-
ble pole, set the two zero frequencies of the type III
compensation less than the LC double-pole frequency
to provide adequate phase boost. Set the two zero fre-
quencies to 80% of the LC double-pole frequency.
Hence:
R1 = ¹ x ^{L x CO x (RO + ESR)}
0.8 x C1
R_L + R_O
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