MAX13037 Datasheet, PDF (15/22 Pages) Maxim Integrated Products – Automotive Contact Monitor and Level Shifters with LDO Regulator

Automotive Contact Monitor and
Level Shifters with LDO Regulator
STATUS REGISTER
IS COPIED TO
SHIFT REGISTER
CS
SHIFT REGISTER IS
COPIED TO COMMAND
REGISTER
CLK
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDI
WTOFF SC2 SC1 SC0 WEN WEND M1 M0 P7 P6 P5 P4 P3 P2 P1 P0
SDO
SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 OT * * * * * * *
* = UNUSED.
Figure 7. SPI Read/Write Example
Serial Peripheral Interface
(CS, SD0, SDI, CLK)
The MAX13037/MAX13038 operate as a Serial Peripheral
Interface (SPI) slave devices. An SPI master accesses
the MAX13037/MAX13038 by reading from a status reg-
ister and writing to a command register. Both registers
are 16 bits long and are accessed most significant bit
(MSB) first.
On the falling edge of CS, the status register is immedi-
ately loaded to an internal shift register and the con-
tents are transferred out of the SDO output on the rising
edge of CLK. Serial data on the SDI input is latched
into the shift register on the falling edge of CLK. On the
rising edge of CS, the contents of the shift register are
copied to the command register (see Figure 7). The
status and command registers are 16 bits wide, so it is
essential to clock a total of 16 bits while CS is low for
the input and output data to be valid. When CS is high,
the SDO output is high-impedance and any transitions
on CLK and SDI are ignored. The INT and OT flags are
cleared on the CS falling edge. Input status changes
occurring during the CS reading/writing operation are
allowed. If a switch status changes when CS is low, the
interrupt is asserted as usual. This allows the part to be
used even if V_LO is disabled provided that the INT out-
put is pulled up to another supply voltage.
Table 1. Status Register
Status Register
The status register contains the status of the switches
connected to IN7 through IN0 and it also contains an
overtemperature warning bit (see Table 1). The status
register is accessed through an SPI-compatible master.
Notes:
Bits 15–8: Switch 7 Through 0 Status (SW7–SW0)
SW7 through SW0 reflect the status of the switches
connected to inputs IN7 through IN0, respectively.
Open switches are returned as a [0] and closed switch-
es are returned as a [1].
Bit 7: Overtemperature Warning (OT)
The OT bit returns a [1] when the internal temperature of
the MAX13037/MAX13038 is above the temperature
warning threshold of +135°C (typ). The OT bit returns a
[0] when the MAX13037/MAX13038 is either below the
temperature threshold, or it has fallen below the tempera-
ture hysteresis level following an overtemperature event.
Bits 6–0: Unused
Bits 6 through 0 are unused and should be ignored.
Command Register
The command register is used to configure the
MAX13037/MAX13038 for various modes of operation
and is accessed by an SPI-compatible master (see
Table 2). The power-on reset (POR) value of the com-
mand register is 0x00.
BIT
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NAME SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 OT — — — — — — —
Table 2. Command Register
BIT
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NAME WTOFF SC2 SC1 SC0 WEN WEND M1 M0 P7 P6 P5 P4 P3 P2 P1 P0
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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