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MAX1292 Datasheet, PDF (15/20 Pages) Maxim Integrated Products – 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Table 5. Data-Bus Output (8 + 4 Parallel
Interface)
PIN HBEN = 0
D0 Bit 0 (LSB)
D1
Bit 1
D2
Bit 2
D3
Bit 3
HBEN = 1
Bit 8
Bit 9
Bit 10
Bit 11 (MSB)
BIPOLAR
(UNI/BIP = 0)
UNIPOLAR
(UNI/BIP = 1)
D4
Bit 4
Bit 11
0
D5
Bit 5
Bit 11
0
D6
Bit 6
Bit 11
0
D7
Bit 7
Bit 11
0
___________Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1290/MAX1292 in external
clock mode and sets INT high. After the power supplies
stabilize, the internal reset time is 10µs, and no conver-
sions should be attempted during this phase. When
using the internal reference, 500µs are required for
VREF to stabilize.
Internal and External Reference
The MAX1290/MAX1292 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.
An internal buffer is designed to provide +2.5V at REF
for both devices. The internally trimmed +1.22V refer-
ence is buffered with a +2.05V/V gain.
Internal Reference
The full-scale range with the internal reference is +2.5V
with unipolar inputs and ±1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
(±100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with
an external capacitor (4.7µF min) connected between
REF and GND to reduce reference noise and switching
spikes from the ADC. To further minimize reference
noise, connect a 0.01µF capacitor between REFADJ
and GND.
External Reference
With the MAX1290/MAX1292, an external reference can
be placed at either the input (REFADJ) or the output
(REF) of the internal reference-buffer amplifier.
VDD = +5V
50kΩ
50kΩ
330kΩ
GND
0.01µF
4.7µF
MAX1290
MAX1292
REFADJ
REF
Figure 7. Reference Voltage Adjustment with External
Potentiometer
Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17kΩ.
When applying an external reference to REF, disable
the internal reference buffer by connecting REFADJ to
VDD. The DC input resistance at REF is 25kΩ.
Therefore, an external reference at REF must deliver up
to 200µA DC load current during a conversion and
have an output impedance less than 10Ω. If the refer-
ence has higher output impedance or is noisy, bypass
it close to the REF pin with a 4.7µF capacitor.
Power-Down Modes
To save power, place the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode using bits D6 and D7 of the
control byte (Tables 1 and 2). In both software power-
down modes, the parallel interface remains active, but
the ADC does not convert.
Standby Mode
While in standby mode, the supply current is 1mA (typ).
The part powers up on the next rising edge on WR and
is ready to perform conversions. This quick turn-on time
allows the user to realize significantly reduced power
consumption for conversion rates below 400ksps.
Shutdown Mode
Shutdown mode turns off all chip functions that draw
quiescent current, reducing the typical supply current
to 2µA immediately after the current conversion is com-
pleted. A rising edge on WR causes the MAX1290/
MAX1292 to exit shutdown mode and return to normal
operation. To achieve full 12-bit accuracy with a 4.7µF
reference bypass capacitor, 500µs is required after
power-up. Waiting 500µs in standby mode, instead of in
full-power mode, can reduce power consumption by a
factor of 3 or more. When using an external reference,
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