MAX1292 Datasheet, PDF (14/20 Pages) Maxim Integrated Products – 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface

400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Digital Interface
Input (control byte) and output data are multiplexed on
a three-state parallel interface. This parallel interface
(I/O) can easily be interfaced with standard µPs. The
signals CS, WR, and RD control the write and read
operations. CS represents the chip-select signal, which
enables a µP to address the MAX1290/MAX1292 as an
I/O port. When high, CS disables the CLK, WR, and RD
inputs and forces the interface into a high-impedance
(high-Z) state.
Input Format
The control byte is latched into the device on pins D7–
D0 during a write command. Table 2 shows the control
byte format.
Output Format
The output format for the MAX1290/MAX1292 is binary in
unipolar mode and two’s complement in bipolar mode.
When reading the output data, CS and RD must be low.
When HBEN = 0, the lower 8 bits are read. With HBEN =
1, the upper 4 bits are available and the output data bits
D7–D4 are set either low in unipolar mode or to the value
of the MSB in bipolar mode (Table 5).
Table 2. Control Byte Format
D7 (MSB)
D6
D5
D4
D3
D2
PD1
PD0
ACQMOD
SGL/DIF
UNI/BIP
A2
D1
D0 (LSB)
A1
A0
Table 3. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
A2
A1
A0
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
0
0
0
+
0
0
1
+
0
1
0
+
0
1
1
+
1
0
0
+
1
0
1
+
1
1
0
+
1
1
1
*Channels CH4–CH7 apply to MAX1290 only.
CH7*
+
COM
-
-
-
-
-
-
-
-
Table 4. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
A2
A1
A0
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
0
0
0
+
-
0
0
1
-
+
0
1
0
+
-
0
1
1
-
+
1
0
0
+
-
1
0
1
-
+
1
1
0
+
1
1
1
-
*Channels CH4–CH7 apply to MAX1290 only.
CH7*
-
+
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