MAX8654_09 Datasheet, PDF (14/17 Pages) Maxim Integrated Products – 12V, 8A 1.2MHz Step-Down Regulator

12V, 8A 1.2MHz
Step-Down Regulator
output voltage divided by the rated output current. ESR
is the total equivalent series resistance (ESR) of the out-
put filtering capacitor. If there is more than one output
capacitor of the same type in parallel, the value of the
ESR in the above equation is equal to that of the ESR of
a single output capacitor divided by the total number of
output capacitors.
The high-switching frequency range of the MAX8654
allows the use of ceramic-output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer function zero is higher
than the unity-gain crossover frequency, f_C, and the
zero cannot be used to compensate for the double pole
created by the output filtering inductor and capacitor.
The double pole produces a gain drop of 40dB and a
phase shift of 180° per decade. The error amplifier must
compensate for this gain drop and phase shift to
achieve a stable high-bandwidth, closed-loop system.
Therefore, use type 3 compensation as shown in Figure
3. Type 3 compensation possesses three poles and two
zeros with the first pole, f_{P1_EA}, located at zero frequen-
cy (DC). Locations of other poles and zeros of the type
3 compensation are given by:
f_{Z1_ EA}
=
2π
x
1
R1
x
C1
f_{Z2 _ EA}
=
2π
1
x R3
x
C3
f_{P3 _ EA}
=
2π
1
x R1
x
C2
f_{P2 _ EA}
=
2π
1
x R2
x
C3
The above equations are based on the assumptions
that C1>>C2, and R3>>R2, which are true in most
applications. Placements of these poles and zeros are
determined by the frequencies of the double pole and
ESR zero of the power-transfer function. It is also a
function of the desired closed-loop bandwidth. The fol-
lowing section outlines the step-by-step design proce-
dure to calculate the required compensation
components for the MAX8654.
Begin by setting the desired output voltage. The output
voltage is set using a resistor-divider from the output to
GND with FB at the center tap (R3 and R4 in Figure 3).
Calculate R4 as:
R4 = ^{0.6 × R3}
V_OUT − 0.6
LX
MAX8654
L
V_OUT
C_OUT
R3
R2
FB
COMP
R1
C1
C3
R4
C2
Figure 3. Type 3 Compensation Network
The zero-cross frequency of the closed loop, f_C, should
be less than 20% of the switching frequency, f_S. Higher
zero-cross frequency results in faster transient
response. It is recommended that the zero-cross fre-
quency of the closed loop should be chosen between
10% and 20% of the switching frequency. Once f_C is
chosen, C1 is calculated from the following equation:
C1 =
2x
π
1.5625 x V_IN
x
R3
x
(1+
R_L
R_O
)
×
f_C
Due to the underdamped nature of the output LC dou-
ble pole, set the two zero frequencies of the type 3
compensation less than the LC double-pole frequency
in order to provide adequate phase boost. Set the two
zero frequencies to 80% of the LC double-pole frequen-
cy. Hence:
R1 = ¹ x ^{L x CO x (RO + ESR)}
0.8 x C1
R_L + R_O
C3 = ¹ x ^{L x CO x (RO + ESR)}
0.8 x R3
R_L + R_O
Set the second compensation pole, f_{P2_EA}, at f_{Z_ESR}
yields:
R2 = ^{CO x ESR}
C3
Set the third compensation pole at the switching fre-
quency. Calculate C2 as follows:
C2 =
1
π × R1 × f_S × 2
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