MAX16922_10 Datasheet, PDF (14/17 Pages) Maxim Integrated Products – 2.2MHz, Dual, Step-Down DC-DC Converters, Dual LDOs, and RESET

2.2MHz, Dual, Step-Down DC-DC
Converters, Dual LDOs, and RESET
Capacitor Selection
Input Capacitors
The input capacitor, CIN1, reduces the current peaks
drawn from the supply and reduces switching noise in
the MAX16922. The impedance of CIN1 at the switch-
ing frequency should be kept very low. Ceramic capac-
itors with X5R or X7R dielectrics are recommended due
to their small size, low ESR, and small temperature
coefficients. Use a 4.7µF ceramic capacitor or an
equivalent amount of multiple capacitors in parallel
between PV1 and ground. Connect CIN1 as close to
the device as possible to minimize the impact of PCB
trace inductance.
Connect a minimum 4.7µF ceramic capacitor between
PV2 to ground, and a 2.2µF ceramic capacitor between
PV3 to ground and PV4 to ground. Since PV2 is cas-
caded from OUT1, the input capacitor connected to
PV2 can be used as part of the total output capacitance
for OUT1.
Step-Down Output Capacitors
The step-down output capacitors are required to keep
the output-voltage ripple small and to ensure regulation
loop stability. These capacitors must have low imped-
ance at the switching frequency. Surface-mount ceram-
ic capacitors are recommended due to their small size
and low ESR. The capacitor should maintain its
capacitance overtemperature and DC bias. Ceramic
capacitors with X5R or X7R temperature characteristics
generally perform well. The output capacitance can be
very low. Place a minimum of 15µF ceramic capaci-
tance from OUTS1 to ground and a minimum of 10µF
from OUTS2 to ground. When the OUT2 output voltage
selection is below 2.35V, the output capacitance should
be increased to prevent instability. For optimum load-
transient performance and very low output ripple, the
output capacitance can be increased. The maximum
output capacitance should not exceed 3.8mF for OUT1
and 2.0mF for OUT2.
LDO Output Capacitors and Stability
Connect a 4.7µF ceramic capacitor between OUT3 and
GND, and a second 4.7µF ceramic capacitor from
OUT4 to GND. When the input voltage of an LDO is
greater than 2.35V, the output capacitor can be
decreased to 2.2µF. The equivalent series resistance
(ESR) of the LDO output capacitors affects stability and
output noise. Use output capacitors with an ESR of
0.1Ω or less to ensure stable operation and optimum
transient response. Connect these capacitors as close
as possible to the device to minimize PCB trace induc-
tance.
Thermal Considerations
The maximum package power dissipation of the
MAX16922 in the 20-pin thin QFN package is 2500mW.
The power dissipated by the MAX16922 should not
exceed this rating. The total device power dissipation is
the sum of the power dissipation of the four regulators:
P_D = P_D1 + P_D2 + P_D3 + P_D4
Estimate the OUT1 and OUT2 power dissipations as
follows:
P_D1
=
I_OUT1
×
V_OUT1
×
1− η
η
P_D2
=
I_OUT2
×
V_OUT2
× ^{1− η}
η
where η is the efficiency (see the Typical Operating
Characteristics section).
Calculate the OUT3 and OUT4 power dissipations as
follows:
P_D3 = I_OUT3 x (V_PV3 – V_OUT3)
P_D4 = I_OUT4 x (V_PV4 – V_OUT4)
The maximum junction temperature of the MAX16922 is
+150°C. The junction-to-case thermal resistance (θ_JC)
of the MAX16922 is 2.7°C/W.
When mounted on a single-layer PCB, the junction to
ambient thermal resistance (θ_JA) is approximately
48°C/W. Mounted on a multilayer PCB, θ_JA is approxi-
mately32°C/W. Calculate the junction temperature of
the MAX16922 as follows:
T_J = T_A x P_D x θ_JA
where T_A is the maximum ambient temperature. Make
sure the calculated value of T_J does not exceed the
+150°C maximum.
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