MAX1630_05 Datasheet, PDF(14/29 Page) Maxim Integrated Products – Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers

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MAX1630_05 Datasheet, PDF (14/29 Pages) Maxim Integrated Products – Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers

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Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

under all operating conditions, including Idle Mode.

The SECFB signal further controls the synchronous

switch timing in order to improve multiple-output cross-

regulation (see Secondary Feedback Regulation Loop

section).

Internal VL and REF Supplies

An internal regulator produces the +5V supply (VL) that

powers the PWM controller, logic, reference, and other

blocks within the IC. This 5V low-dropout linear regula-

tor supplies up to 25mA for external loads, with a

reserve of 25mA for supplying gate-drive power.

Bypass VL to GND with 4.7ÂµF.

Important: Ensure that VL does not exceed 6V.

Measure VL with the main output fully loaded. If it is

pumped above 5.5V, either excessive boost diode

capacitance or excessive ripple at V+ is the probable

cause. Use only small-signal diodes for the boost cir-

cuit (10mA to 100mA Schottky or 1N4148 are pre-

ferred), and bypass V+ to PGND with 4.7ÂµF directly at

the package pins.

The 2.5V reference (REF) is accurate to Â±2% over tem-

perature, making REF useful as a precision system ref-

erence. Bypass REF to GND with 1ÂµF minimum. REF

can supply up to 5mA for external loads. (Bypass REF

with a minimum 1ÂµF/mA reference load current.)

However, if extremely accurate specifications for both

the main output voltages and REF are essential, avoid

loading REF more than 100ÂµA. Loading REF reduces

the main output voltage slightly, because of the refer-

ence load-regulation error.

When the 5V main output voltage is above 4.5V, an

internal P-channel MOSFET switch connects CSL5 to

VL, while simultaneously shutting down the VL linear

regulator. This action bootstraps the IC, powering the

internal circuitry from the output voltage, rather than

through a linear regulator from the battery.

Bootstrapping reduces power dissipation due to gate

charge and quiescent losses by providing that power

from a 90%-efficient switch-mode source, rather than

from a much less efficient linear regulator.

Boost High-Side Gate-Drive Supply

(BST3 and BST5)

Gate-drive voltage for the high-side N-channel switches

is generated by a flying-capacitor boost circuit

(Figure 2). The capacitor between BST_ and LX_ is

alternately charged from the VL supply and placed par-

allel to the high-side MOSFETâs gate-source terminals.

On start-up, the synchronous rectifier (low-side

MOSFET) forces LX_ to 0V and charges the boost

capacitors to 5V. On the second half-cycle, the SMPS

turns on the high-side MOSFET by closing an internal

switch between BST_ and DH_. This provides the nec-

essary enhancement voltage to turn on the high-side

switch, an action that âboostsâ the 5V gate-drive signal

above the battery voltage.

Ringing at the high-side MOSFET gate (DH3 and DH5)

in discontinuous-conduction mode (light loads) is a nat-

ural operating condition. It is caused by residual ener-

gy in the tank circuit, formed by the inductor and stray

capacitance at the switching node, LX. The gate-drive

negative rail is referred to LX, so any ringing there is

directly coupled to the gate-drive output.

Current-Limiting and Current-Sense

Inputs (CSH and CSL)

The current-limit circuit resets the main PWM latch and

turns off the high-side MOSFET switch whenever the

voltage difference between CSH and CSL exceeds

100mV. This limiting is effective for both current flow

directions, putting the threshold limit at Â±100mV. The

tolerance on the positive current limit is Â±20%, so the

external low-value sense resistor (R1) must be sized for

80mV/IPEAK, where IPEAK is the required peak inductor

current to support the full load current, while compo-

nents must be designed to withstand continuous cur-

rent stresses of 120mV/R1.

For breadboarding or for very-high-current applications,

it may be useful to wire the current-sense inputs with a

twisted pair, rather than PC traces. (This twisted pair

neednât be anything special; two pieces of wire-wrap

wire twisted together are sufficient.) This reduces the

possible noise picked up at CSH_ and CSL_, which can

cause unstable switching and reduced output current.

The CSL5 input also serves as the ICâs bootstrap sup-

ply input. Whenever VCSL5 > 4.5V, an internal switch

connects CSL5 to VL.

Oscillator Frequency and

Synchronization (SYNC)

The SYNC input controls the oscillator frequency. Low

selects 200kHz; high selects 300kHz. SYNC can also

be used to synchronize with an external 5V CMOS or

TTL clock generator. SYNC has a guaranteed 240kHz

to 350kHz capture range. A high-to-low transition on

SYNC initiates a new cycle.

300kHz operation optimizes the application circuit for

component size and cost. 200kHz operation provides

increased efficiency, lower dropout, and improved

load-transient response at low input-output voltage dif-

ferences (see Low-Voltage Operation section).

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