MAX15068 Datasheet, PDF (14/17 Pages) Maxim Integrated Products – Dual ORing, Single Hot-Swap Controller

MAX15068
Dual ORing, Single Hot-Swap Controller with
Accurate Current Monitoring
The device turns off the output when V_ON falls below
V_{UV_REF} (1.22V - V_{ON_HYS}). An external resistive
divider from CSP to ON and ground is used to set
the undervoltage-lockout threshold to any desired level
between V_UVLO and 18V. Pulling the ON pin voltage
below 0.6V resets the electronic circuit breaker.
Monitoring
Analog Current Monitor Output
IPMON monitors the current delivered to the system. IP-
MON has a 0 to 1.8V output voltage range. IPMON moni-
tors the system input current. The device does not have a
power monitor.
The voltage at IPMON in this case is proportional to the
input current by the following equation:
V_IPMON = G_I x R_IPMON x (V_CSP - V_CSN)
where G_I = 0.3mS/V and R_IPMON is the resistor to set the
voltage overall voltage gain for IPMON.
When connected as shown in the Typical Application
Circuit, IPMON monitors the input system current. Leave
IPMON unconnected if the function is not used.
The maximum output of V_IPMON should be limited to 1.8V
to get best accuracy using proper R_IPMON resistor value.
Output Signals
Fault Status Output (FAULT)
FAULT is an open-drain output that is internally pulled high
by a 10µA current source to a diode below V_S, and can be
pulled above V_S using an external pullup. FAULT asserts
low when the circuit breaker is tripped after an overcurrent
fault timeout. Leave FAULT unconnected if unused.
Power-Good Output (PG)
Internal circuitry monitors the hot-swap MOSFET gate
overdrive between the GATE and OUT pins and the volt-
age at the OUT pin. The power-good status for the supply
is reported by the PG open-drain output. It is normally
pulled high by an external pullup resistor or the internal
10µA pullup. The power-good output asserts low when
the gate overdrive exceeds 4.2V during the GATE startup
and the voltage at the OUT pin exceeds (0.9 x V_CSP). The
PG signal is delayed by 16ms once conditions for power-
good are met.
Fault Management
Autoretry
When an overcurrent fault is latched after tripping the
circuit breaker, the FAULT pin is asserted low. Only the
hot-swap MOSFET is turned off, and the ideal diode
MOSFETs are not affected. The latched fault is reset
automatically after a cool-off timing cycle as described in
the Startup Timer (CDLY) section. At the end of the cool-
off period, the fault latch is cleared and FAULT pulls high.
The GATE pin voltage is allowed to start up and turn on
the hot-swap MOSFET. If the output short persists, the
supply powers up into a short with active current limiting
until the circuit breaker times out and FAULT again pulls
low. A new cool-off cycle begins with CDLY ramping down
with a 2µA current. The whole process repeats itself until
the output short is removed. Since t_CB and t_COOL are a
function of CDLY capacitance, C_CDLY, the autoretry duty
cycle is equal to 0.1%, irrespective of C_CDLY.
Applications Information
Prioritizing Supplies with PC
Figure 2 shows an ORing application where a resistive
divider connected from IN1 at the PC pin controls the turn-
on of the ORing MOSFET, MD2, in the IN2 supply path.
When the IN1 supply voltage falls below 4.5V, it turns on
the ORing MOSFET, MD2, causing the ORing output to
be switched from the main 5.0V supply at IN1 to the aux-
iliary 5.0V supply at IN2. This configuration permits the
load to be supplied from a lower IN1 supply as compared
to IN2 until IN1 falls below the MD2 turn-on threshold. The
threshold value used should not allow the IN1 supply to
be operated at more than one diode voltage below IN2.
Otherwise, MD2 conducts through the MOSFET’s body
diode. The resistive divider connected from CSP at the
ON pin provides the undervoltage threshold of 2.6V for
the ORing output supply.
Table 1. Electronics Circuit-Breaker Threshold Programming
CB PIN CONNECTION
CB = GND
ELECTRONIC CIRCUIT-BREAKER THRESHOLD (V_CSP - V_CSN) [mV]
35
CB = Hi-Z (unconnected)
50
CB = V_S
65
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