MAX1454_11 Datasheet, PDF(14/25 Page) Maxim Integrated Products – Precision Sensor Signal Conditioner with Overvoltage Protection

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MAX1454

Precision Sensor Signal Conditioner

with Overvoltage Protection

To write to a flash memory location in burst mode, the

user simply writes DHR[3:0], followed by DHR[7:4].

Since the internal counter keeps track of the memory

address, there is no need to send address information

to the part. After DHR[7:4] is written, a write command

to the flash memory is automatically generated, the data

in DHR[7:0] is written to the memory, and the address

counter is incremented. If the user wishes to skip certain

memory locations, first exit burst mode (by writing a 0 to

BURSTEN), then program a new starting address. The

user can now reenable burst mode again.

During burst read operations, the device waits for a

read command before sending out data whose address

is derived from the internal counter. To start burst read

mode, first program the flash memory address into

IEEA[10:0]. Next, write a 1 to BURSTEN to enable burst

mode. The IRSP register must then be programmed

to 0 (through an IRSA = 8 command). Then, send the

flash memory read (RdEEP) CRIL command to initiate

an internal read; the device sends the contents of the

flash memory out of the DIO/OUT pin through the serial

interface. Similar to the burst write operation, the burst

read operation does not skip memory locations. To skip

memory locations, first write a zero to BURSTEN to end

burst mode. Next, change the memory address bits

using the corresponding command bytes. Once the

desired starting address is loaded, reenable burst mode

to resume burst reading.

Always disable burst mode (IRSD = 0000 when IRSA =

1101) after burst reading/writing all the locations. This is

necessary to continue in digital programming mode after

all the burst read/writes are complete.

Note: Use burst mode to program a maximum of 1024

locations. Care must be taken to avoid additional writes

to prevent unintentionally rewriting locations. The internal

address counter wraps around to address 0x000 after

reaching address 0x3FF.

Table 2. Registers

CONFIG1

CONFIG2

ODAC

OTCDAC

FSODAC

FSOTCDAC

PWRUPCFG

DESCRIPTION

Configuration Register 1

Configuration Register 2

Offset DAC

Offset Temperature Coefficient DAC

Full-Span Output DAC

Full-Span Output Temperature Coefficient DAC

Power-Up Configuration

Table 3. Configuration Register 1 (CONFIG1[15:0])

BIT

15:11

8:5

4:3

NAME

PGA[4:0]

PGA Sign

IRO Sign

IRO[3:0]

CMRATIO[1:0]

Reserved

ODAC Sign

OTCDAC Sign

DESCRIPTION

Programmable-gain amplifier setting

Logic 1 inverts IN- and IN+ polarity

Logic 1 for positive input-referred offset (IRO), logic 0 for negative input-referred offset (IRO)

Input-referred coarse-offset adjustment

Bridge driver current-mirror ratio

Set to logic 0

Logic 1 for positive offset DAC output, logic 0 for negative offset DAC output

Logic 1 for positive offset TC DAC output, logic 0 for negative offset TC DAC output

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